Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

A method for forming a semiconductor structure includes the following operations. A substrate is formed. The substrate includes a body part and a protrusion part located on a surface of the body part. A gate electrode located on the body part and distributed around sidewalls of the protrusion part is formed. A first doped region and a second doped region located in the body part and distributed at two opposite sides of the gate electrode are formed.

A plurality of first trenches is formed in a cell region and a second trench is formed in an outer peripheral region. A gate electrode and a first field plate electrode are formed in each of the plurality of first trenches, and a second field plate electrode is formed in the second trench. For example, in a drift region formed in the outer peripheral region, a p-type column region is formed in a portion sandwiched, in a Y direction, by a portion, which is located between two of the plurality of first trenches arranged next to each other, and the second trench.

A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

A method of forming an SRAM cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate transistor, and a second vertical pass-gate transistor over a semiconductor substrate. The method includes forming a first conductive trace over a top surface of the first vertical pull-down transistor and the first vertical pass-gate transistor, forming a second conductive trace over a top surface of the second vertical pull-down transistor and the second vertical pass-gate transistor, and forming a first vertical pull-up transistor over a first portion of the first conductive trace. The method also includes forming a second vertical pull-up transistor over a first portion of the second conductive trace. The method also includes forming a first via over the first conductive trace and forming a second via over the second conductive trace.

A semiconductor device includes an array of needle-shaped trenches extending into a semiconductor substrate. The semiconductor device further includes a gate trench grid extending into the semiconductor substrate. A gate electrode of a transistor structure is located within the gate trench grid. A gate wiring structure of the transistor structure is connected to the gate electrode of the transistor structure. A field electrode located within at least one needle-shaped trench of the array of needle-shaped trenches is connected to the gate wiring structure of the transistor structure.

A SiC semiconductor device includes SiC chip having main surface that includes first surface, second surface hollowed in thickness direction at first depth outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a transistor structure formed at an inward portion of the first surface, the transistor structure including a trench gate structure that has a second depth less than the first depth and a trench source structure that has a third depth exceeding the second depth and that adjoins the trench gate structure in one direction, and a dummy structure formed at a peripheral edge portion of the first surface, the dummy structure including a plurality of dummy trench source structures which have the third depth and adjoin each other in the one direction.

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming an silicon pillar on the substrate; preprocessing the silicon pillar, to form an active pillar including a first segment, a second segment, and a third segment, where the second segment includes a first sub-segment and a second sub-segment, and a cross-sectional area of the second sub-segment is smaller than that of the first sub-segment; forming a gate oxide layer; and forming a word line structure surrounding the second segment, where the word line structure includes a first word line structure and a second word line structure that are made of different materials.

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array on the substrate, where the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially, and along a second direction, a cross-sectional area of the second segment is smaller than those of the first segment and the third segment; forming a gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a gate dielectric layer on the gate oxide layer, where the gate dielectric layer is shorter than the gate oxide layer, and is close to the third segment.

Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.