A semiconductor device includes a semiconductor part, first to third electrodes, and first and second control electrodes. The semiconductor part is provided between the first and second electrodes. On the second electrode side of the semiconductor part, the first control electrode and the third electrode are provided in a first trench, and the second control electrode is provided in a second trench. The first control electrode is provided between the second and third electrode. In a first direction from the first control electrode toward the second control electrode, the first trench has first and second widths. The first width is a combined width of the third electrode and insulating portions provided on both sides of the third electrode. The second width is a combined width of the first control electrode and the gate insulating films on both sides thereof. The first width is greater than the second width.

A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 10.sup.18 cm.sup.−3. A semiconductor structure and a manufacturing method are also provided.

A vertical FET includes a channel fin between a bottom source/drain (S/D) region and a top S/D region, a gate upon a sidewall of the channel fin, a top metallization upon the top S/D region, a first contact metallization connected to the gate, a second contact metallization connected to the bottom S/D region, a first vertical liner between a portion of the gate and the first contact metallization, and a second vertical liner between the top metallization and the second contact metallization. The vertical FET may be fabricated by forming a self-aligned block and utilizing the self-aligned block to e.g., prevent gate to gate shorting during replacement gate formation or processing.

Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure. The method can further include forming a vertical opening in the layer stack and removing the sacrificial layer through the vertical opening to separate the lower and upper vertical channel structures.

Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.

The present disclosure provides a method for manufacturing a semiconductor structure having a vertical fin with an oxidized sidewall. The method of manufacturing the semiconductor structure includes the steps of providing a substrate having a bottom source/drain and a bottom cathode/anode; forming a channel fin on the bottom source/drain of the substrate and a vertical fin on the cathode/anode of the substrate; forming a top source/drain on the channel fin and a top cathode/anode on the vertical fin; forming a gate structure on the channel fin; and forming an oxidized sidewall on the vertical fin.

An electrode structure of a back electrode including metal layers laminated in the following order: a Ti layer, a Ni layer, and a Ag alloy layer. The Ag alloy layer includes an Ag alloy and an addition metal M selected from Sn, Sb, and Pd. The electrode structure is configured such that when subjected to elemental analysis with an X-ray photoelectron spectrometer in the depth direction from the Ag alloy layer to the Ni layer, on the boundary between the Ni layer and the Ag alloy layer, an intermediate region where spectra derived from all the metals, Ni, Ag, and the addition element M, can be detected is observable, and, when each metal content in the intermediate region is converted based on the spectra derived from all the metals Ni, Ag, and the addition element M, the maximum of the addition element M content is 5 at % or more.

Provided are a semiconductor device and a method for manufacturing same. The device comprises: a substrate, a first insulating layer on the substrate, a plurality of trenches formed in the substrate, a nucleation layer arranged on one side wall of each trench, and a first semiconductor layer formed along the trenches by means of the nucleation layer. The present disclosure facilitates the achievement of one of the following effects: achieving a high height-width ratio and a high integration density, reducing an on-resistance, improving a threshold voltage, achieving a normally-off state, and providing a semiconductor device that has a high power and a high reliability, is suitable for a planarization process, is provided with an easy preparation method, and reduces costs.

Embodiments of a method for forming a three-dimensional (3D) memory device includes the following operations. First, a channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. A semiconductor channel is formed by filling the channel hole with a channel-forming structure. The plurality of first layers is removed. A plurality of conductor layers is formed from the plurality of second layers. Further, a gate-to-gate dielectric layer is formed between the adjacent conductor layers, the gate-to-gate dielectric layer including at least one sub-layer of silicon oxynitride.

A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.