A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

For the manufacturing of a vertical conduction silicon carbide electronic device, a work wafer, which has a silicon carbide substrate having a work face, is processed. A rough face is formed from the work face of the silicon carbide substrate. The rough face has a roughness higher than a threshold. A metal layer is deposited on the rough face and the metal layer is annealed, thereby causing the metal layer to react with the silicon carbide substrate, forming a silicide layer having a plurality of protrusions of silicide.

A semiconductor device includes a semiconductor chip having a principal surface, a first-conductivity-type drift region, a second-conductivity-type body region, a first-conductivity-type source region, a plurality of trench source structures that are formed at the principal surface so as to cross the source region and the body region and so as to reach the drift region and that are arranged with intervals therebetween in a first direction, a second-conductivity-type body connection region formed in a region between two of the trench source structures that are adjacent in the surface layer portion of the body region so as to be electrically connected to the body region, and a first-conductivity-type source connection region formed in a region between two of the trench source structures that are adjacent in a region differing from the body connection region in the surface layer portion of body region so as to be electrically connected to source region.

A vertical field effect transistor includes a first epitaxial region in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate, a second epitaxial region above the first epitaxial region having a horizontal thickness that is larger than a horizontal thickness of the first epitaxial region. The first epitaxial region and the second epitaxial region form a top source/drain region of the semiconductor structure. The first epitaxial region has a first doping concentration and the second epitaxial region has a second doping concentration that is lower than the first doping concentration. A top spacer, adjacent to the first epitaxial region and the second epitaxial region, is in contact with a top surface of a high-k metal gate stack located around the channel fin and in contact with a top surface of a first dielectric layer disposed between adjacent channel fins.

A semiconductor device includes: a semiconductor chip having a bottom surface having a first area and a first side surface; and an electrode provided below the semiconductor chip, the electrode having a first top surface and a second side surface, and the electrode containing an electrically conductive material, wherein the first top surface has a second area larger than the first area, and at least a part of the first top surface is in contact with the bottom surface.

Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

A vertical field-effect transistor device includes a substrate comprising a semiconductor material, and a set of fins formed from the semiconductor material and extending vertically with respect to the substrate. The vertical field-effect transistor device further includes gate structures disposed on the substrate and on a portion of sidewalls of the set of fins, spacers disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins, source/drain regions disposed over top portions of the set of fins, and a metal liner disposed adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions. A portion of the source/drain regions is configured to have a lateral width less than a width between adjacent gate structures on the respective fin.

The fabrication method for a silicon carbide semiconductor device according to this disclosure includes a step of forming a dielectric film over part of a silicon carbide layer, a step of forming an ohmic electrode adjoining the dielectric film on the silicon carbide layer, a step of removing an oxidized layer on the ohmic electrode, a step of forming a mask with its opening on the side opposite to the side where the ohmic electrode is adjoining the dielectric film on the ohmic electrode having the oxidized layer removed and on the dielectric film, and a step of wet etching of a film to be etched with hydrofluoric acid with the mask formed. With the fabrication method for a silicon carbide semiconductor device described in this disclosure, it is possible to fabricate a silicon carbide semiconductor device with reduced failure.

A field-effect transistor includes an n-type semiconductor layer that includes a Ga.sub.2O.sub.3-based single crystal and a plurality of trenches opening on one surface, a gate electrode buried in each of the plurality of trenches, a source electrode connected to a mesa-shaped region between adjacent trenches in the n-type semiconductor layer, and a drain electrode directly or indirectly connected to the n-type semiconductor layer on an opposite side to the source electrode.