A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

Disclosed is a method for manufacturing a conducting path in a doped region, comprising: forming a dielectric layer on a semiconductor layer which includes the doped region; forming an opening in the dielectric layer; forming a side wall on sidewall of the opening; etching the semiconductor layer through the opening to form a conduction hole extending to the doped region; filling the conduction hole with conductive material to form a conducting path, wherein the side wall reduces a transverse dimension of the conducting path. According to the method for manufacturing the conducting path in the doped region in the present disclosure, by forming the side wall on sidewall of the opening in the dielectric layer, the transverse dimension of the opening in the dielectric layer is reduced, thereby the semiconductor layer is etched with a narrower opening to obtain the conduction hole with a smaller size, device performance is improved.

A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

An object is to provide a semiconductor device that can prevent organic contamination of an electrode including a plurality of laminated metal layers. A semiconductor device includes: a semiconductor substrate; and an electrode including a plurality of layers laminated on a principal surface of the semiconductor substrate. The electrode includes: a first metal layer in contact with the principal surface of the semiconductor substrate, the first metal layer containing Al; an oxide layer formed on a surface of the first metal layer, the oxide layer containing a metal and oxygen; and a second metal layer formed on a surface of the oxide layer. Concentrations of the oxygen in the oxide layer are higher than or equal to 8.0×10.sup.21/cm.sup.3 and lower than or equal to 4.0×10.sup.22/cm.sup.3.

A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

Embodiments of the invention include a vertical field-effect transistor (VTFET) inverter. The VTFET inverter may include a p-channel field-effect transistor (P-FET) with a P-FET top source/drain and a P-FET bottom source/drain. The VTFET inverter may also include an n-channel field-effect transistor (N-FET) comprising an N-FET top source/drain and a N-FET bottom source/drain. The VTFET inverter may also include a buried contact located at a boundary between the P-FET bottom source/drain and the N-FET bottom source/drain. The VTFET inverter may also include a Vout contact electrically connected to one of the P-FET bottom source/drain and the N-FET bottom source/drain.

VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

A semiconductor structure includes a gate stack surrounding a semiconductor channel; a first semiconductor source/drain; a first metallic contact that touches the first source/drain; a second semiconductor source/drain; and a second metallic contact that touches the second source/drain. A conductive path length from the channel to the first metallic contact through the first source/drain is smaller than a conductive path length from the channel through the second source/drain to the second metallic contact. The second source/drain includes a bypass layer that touches the second metallic contact, and the bypass layer includes a metastable alloy of two or more elements of semiconductors and dopants.