A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.

A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.

A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region.

The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the Al.sub.xGa.sub.1-xN layer 12 satisfy the following equation

t≧α(a)x.sup.β(a)

Where α is expressed as Log (α)=p.sub.0+p.sub.1 log (a)+p.sub.2{log (a)}.sup.2 (p.sub.0=7.3295, p.sub.1=−3.5599, p.sub.2=0.6912) and β is expressed as β=p′.sub.0+p′.sub.1 log (a)+p′.sub.2{log (a)}.sup.2 (p′.sub.0=−3.6509, p′.sub.1=1.9445, p′.sub.2=−0.3793).

Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions. The first RESURF region extends from a source end toward a drain end of the LDMOS device. The first RESURF region is adjacent to a forms a metallurgical junction with the drift region. The second RESURF layer extends from the drain end toward the source end of the LDMOS device. The second RESURF layer has an end that is longitudinally between the body contact and the source end of the first RESURF layer. A distance between the end of the second RESURF layer and the body contact is greater than a vertical distance between the end of the second RESURF layer and the body contact. A maximum electric field between the second RESURF layer and the body contact can be advantageously reduced with this geometry.

Certain embodiments provide a semiconductor device of an example including a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, a drain electrode and source electrode provided on the semiconductor layer, a gate electrode provided between the drain electrode and the source electrode on the semiconductor layer, and a heat transfer unit provided so as to fill a groove which penetrates the semiconductor layer right below the drain electrode till reaches the semiconductor substrate. The heat transfer unit includes a material different from that of the drain electrode and having thermal conductivity higher than that of the semiconductor substrate and the semiconductor layer under an operating temperature of the semiconductor device.

A semiconductor device having: a substrate; a nitride semiconductor layer including a first semiconductor layer made of GaN or In.sub.xGa.sub.1-xN (0<x≦1) and formed on the substrate and a second semiconductor layer containing Al and formed on the first semiconductor layer; and a protective film formed on the set of nitride semiconductor layers. The nitride semiconductor layer has an active section and an inactive section surrounding the active section, and a portion of the second semiconductor layer has been removed from the inactive section.

A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.

In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.

Among multiple drain regions, a contact surface area between second contacts and a drain region most proximal to a central portion of an element region in a second direction is less than a contact surface area between second contacts and a drain region disposed on an outermost side of the element region in the second direction. The multiple drain regions are arranged in the second direction.