A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a stopper layer on the first insulating film; covering the stopper layer and the first insulating film with a second insulating film; preparing a first mask having an edge that overlaps with the stopper layer; depositing a seed layer on the first mask and the second insulating film that is exposed from the first mask; preparing a second mask having an edge that overlaps with the stopper layer, the edge of the first mask retreating from the edge of the second mask; forming an upper layer on the seed layer by electro-plating a metal so as not to overlap with the first mask; and removing the seed layer exposed from the upper layer by etching.

A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.

In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Disclosure is a method for manufacturing a semiconductor device. The method includes forming a source electrode and a drain electrode on a nitride semiconductor layer formed on a main surface of a SiC substrate, forming a gate electrode having a laminated structure including a Ni layer and an Au layer on the Ni layer between the source electrode and the drain electrode on the nitride semiconductor layer and forming a first metal film having the same laminated structure as the gate electrode in a region adjacent to the source electrode with an interval therebetween, forming a second metal film to contact with the source electrode and the first metal film, forming a hole being continuous with the first metal film from a back surface of the SiC substrate, and forming a metal via being continuous with the first metal film from the back surface in the hole.

A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a source region and a drain region in a substrate, a gate structure and a metallic line. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate, and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metallic line is located above the source and drain regions and the gate structure and electrically connected to the drain region or the source region. The source region includes a doped region having a break region located between two opposite ends of the doped region. The metallic line extends from the drain region, across the gate structure and across the break region and beyond the source region.

There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

In order to reduce costs as well as to effectively dissipate heat in certain RF circuits, a semiconductor device of the circuit can include one or more active devices such as transistors, diodes, and/or varactors formed of a first semiconductor material system integrated onto (e.g., bonded to) a base substrate formed of a second semiconductor material system that includes other circuit components. The first semiconductor material system can, for example, be the III-V or III-N semiconductor system, and the second semiconductor material system can, for example be silicon.

A normally-off field effect transistor device includes a gate electrode structure having a first insulating film, a charge-accumulation gate electrode, a second insulating film and a gate electrode deposited one by one on a semiconductor, and a first capacitor formed by capacitive coupling between the charge-accumulation gate electrode and a source electrode. A charge is accumulated on the charge-accumulation gate electrode by a first current flowing through the first capacitor. The gate electrode structure further includes a stacked film having a third insulating film and a first semiconductor layer provided between the source electrode and the charge-accumulation gate electrode, with at least part of the first current flowing through the stacked film.

An apparatus includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a conductive metallic region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer. Additionally, the conductive metallic region is structured and arranged to extend a limited length parallel to said group III-Nitride barrier layer.