A semiconductor device that achieves both miniaturization and high breakdown voltage is disclosed. The semiconductor device has a gate electrode G1 formed in a trench TR extending in Y direction and a plurality of column regions PC including column regions PC1 to PC3 formed in a drift region ND. The column regions PC1, PC2 and PC3 are provided in a staggered manner to sandwich the trench TR. An angle θ1 formed by a line connecting the centers of the column regions PC1 and PC2 and a line connecting the centers of the column regions PC1 and PC3 is 60 degrees or more and 90 degrees or less.

A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a nitride region, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to sixth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The sixth partial region is between the fifth and second partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion is in contact with the fifth partial region. The nitride region includes a first nitride portion being in contact with the sixth partial region. The first insulating member includes a first insulating region between the third partial region and the first electrode portion.

A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.

A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern. The first separation pattern is wider than the second separation pattern, and the first gate insulating layer extends between the first gate electrode and the first separation pattern, and contacts side and top surfaces of the first separation pattern.

A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 10.sup.18 cm.sup.−3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the barrier layer, a first layer adjacent to a first side of the p-type semiconductor layer without extending to a second side of the p-type semiconductor layer, and a second layer adjacent to the second side of the p-type semiconductor layer without extending to the first side of the p-type semiconductor layer.

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.

The semiconductor device including an active pattern on a substrate and extending in a first direction, a gate structure on the active pattern, including a gate electrode extending in a second direction different from the first direction, a source/drain pattern on at least one side of the gate structure, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern, wherein with respect to an upper surface of the active pattern, a height of an upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact, and the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact, may be provided.

A semiconductor device includes a channel layer configured to include a first nitride semiconductor containing gallium (Ga) and a first crystal dislocation density, and a barrier layer provided over a first surface side of the channel layer, and configured to include a second nitride semiconductor containing aluminum (Al) and a second crystal dislocation density, wherein the second crystal dislocation density is larger than the first crystal dislocation density.