A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.

The present invention introduces a new shielded gate trench MOSFETs wherein epitaxial layer having special multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing in a direction from substrate to body regions, wherein each of the MSE layers has uniform doping concentration as grown. Specific on-resistance is significantly reduced with the special MSE structure. Moreover, in sore preferred embodiment, an MSO (multiple stepped oxide) structure is applied to the shielded gate structure to further reduce the specific on-resistance and enhance device ruggedness.

According to one embodiment, a semiconductor device includes a first crystal region, a second crystal region, a third crystal region, and a fourth crystal region. The first crystal region includes magnesium and Al.sub.x1Ga.sub.1-x1N (0≤x1<1). The second crystal region includes Al.sub.x2Ga.sub.1-x2N (0<x2≤1). The third crystal region is provided between the first crystal region and the second crystal region. The third crystal region includes oxygen and Al.sub.x3Ga.sub.1-x3N (0≤x3≤1 and x3<x2). The fourth crystal region is provided between the third crystal region and the second crystal region. The fourth crystal region includes Al.sub.x4Ga.sub.1-x4N (0≤x4<1 and x4<x2).

The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

A semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type, a source region and a body contact region in the second semiconductor region. The semiconductor device also includes a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region, a gate dielectric layer overlying both the channel region and a portion of the first semiconductor region, and a gate electrode overlying the gate dielectric layer. The semiconductor device further includes a conformal conductive layer covering an upper surface of the body contact region and a side surface of the source region.

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second contact openings on the n- and p-type S/D regions, respectively, forming a carbon-based layer in the first and second contact openings, performing a remote plasma treatment with radicals on the carbon-based layer to form a remote plasma treated layer, selectively removing a portion of the remote plasma treated layer, forming a p-type work function metal (pWFM) silicide layer on the p-type S/D region, and forming an n-type work function metal (nWFM) silicide layer on the pWFM silicide layer and on the n-type S/D region.

A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source/drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source/drain contact electrically connected to, and on, the source/drain region, and a silicide layer between the source/drain region and the source/drain contact which contacts contact with the second doping layer and extends to an upper surface of the source/drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer.

A nitride semiconductor device includes a substrate, a drift layer and a block layer sequentially provided above the substrate, a gate opening penetrating through a block layer and reaching a drift layer, an electron transit layer and an electron supply layer sequentially provided above the block layer and along the inner surface of the gate opening, a gate electrode provided to cover the gate opening, a source opening penetrating through an electron supply layer and an electron transit layer and reaching the block layer, a source electrode provided in the source opening, and a drain electrode on the rear surface side of the substrate. Seen in a plan view, at least part of an outline of an end of the gate opening in the longitudinal direction follows an arc or an elliptical arc.

In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.

A bonded semiconductor device including an epitaxial layer, and a support substrate made of a material different from that of the epitaxial layer and bonded to the epitaxial layer. Any one of the epitaxial layer and the support substrate has a bonding surface with a radial pattern including recesses or protrusions radially spreading from a certain point on the bonding surface as a center.