HIGH ELECTRON MOBILITY TRANSISTOR WITH REDUCED ACCESS RESISTANCE AND METHOD FOR MANUFACTURING A HIGH ELECTRON MOBILITY TRANSISTOR WITH REDUCED ACCESS RESISTANCE

Abstract

A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.

Claims

1. A high electron mobility transistor comprising: a stack of layers comprising a passivation layer and a heterojunction comprising a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; a n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at a level of a recess formed in the stack of layers, said source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first semiconductor layer and the second semiconductor layer, said source metal contact and/or said drain metal contact further having a lateral face, the n+ doped zone extending from the lateral face of the source metal contact and/or from the lateral face of the drain metal contact to the gate electrode over a length comprised between 300 and 1000 nm.

2. The transistor according to claim 1, wherein the n+ doped zone is an implanted zone having a spatial doping profile of gaussian type along the direction normal to the plane of the layers.

3. The transistor according to claim 1, wherein the lower face of the source metal contact and/or the lower face of the drain metal contact is below the two-dimensional electron gas.

4. The transistor according to claim 1, wherein a distance between the gate electrode and the n+ doped zone is comprised between 200 nm and 400 nm.

5. The transistor according to claim 1, wherein the n+ doped zone is doped with a Si or Ge type dopant with a concentration greater than or equal to 10.sup.20 cm.sup.−3.

6. The transistor according to claim 1, wherein the first semiconductor layer comprises AlGaN and the second semiconductor layer comprises GaN.

7. A method for manufacturing a high electron mobility field effect transistor comprising: providing a high mobility electron transistor substrate comprising a stack of layers comprising a passivation layer and a heterojunction comprising a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof; forming an n+ doped zone by ion implantation inside the heterojunction and activation annealing of the n+ doped zone; depositing a dielectric layer in contact with the passivation layer; etching the stack of layers and the dielectric layer to form a recess directly in line and in contact with the n+ doped zone, said recess being configured to accommodate a source and/or drain metal contact, the lower face of the recess being situated below the interface between the first semiconductor layer and the second semiconductor layer; depositing a metal layer intended to form the source metal contact and/or the drain metal contact; chemical mechanical polishing the metal layer to obtain a planarized upper surface of the source contact and/or an upper surface of the drain contact, and defining and depositing a gate electrode, the n+ doped zone extending from a lateral face of the source metal contact and/or from a lateral face of the drain metal contact to the gate electrode over a length comprised between 300 and 1000 nm.

8. The manufacturing method according to claim 7, wherein the forming of the n+ doped zone comprises a mono-energy implantation of Si or Ge ions, with an implantation energy comprised between 60 keV and 80 keV.

9. The manufacturing method according to claim 7, wherein the activation annealing of the n+ doped zone comprises a heat treatment at 975° C. for 10 hours, at 1000° C. for three hours or at 1050° C. for one hour.

10. The manufacturing method according to claim 7, further comprising a photolithography step to define an implantation zone intended to accommodate the n+ doped zone.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0070] Other characteristics and benefits of the invention will become clear from the description that is given thereof below, as an indication and in no way limiting, with reference to the appended figures, among which:

[0071] FIG. 1 illustrates a schematic sectional view of a HEMT according to the prior art;

[0072] FIG. 2 represents a TEM image of a HEMT according to the prior art and comprising a “full-recess” type contact with overflowing metal;

[0073] FIG. 3 represents a schematic sectional view of a HEMT according to the prior art and comprising a source or drain contact produced by etching and re-epitaxy;

[0074] FIG. 4 represents a schematic sectional view of a part of a HEMT according to the invention;

[0075] FIG. 5 represents a TEM section of a transistor according to the invention;

[0076] FIG. 6 represents the implantation profile of Si ions according to one embodiment of the transistor according to the invention;

[0077] FIG. 7 schematically illustrates the method according to the invention;

[0078] FIGS. 8a to 8p illustrate the results of the different steps of the method according to the invention of FIG. 7;

[0079] FIG. 9 illustrates the variation in the effective contact resistance of the transistor, R.sub.C, as a function of the variation in operating temperature of the device according to the invention;

[0080] FIG. 10 illustrates the variation in the transition resistance R.sub.T as a function of the operating temperature of the device according to the invention;

[0081] FIG. 11 illustrates the variation in the resistance of the n+ doped zone as a function of the operating temperature of the device according to the invention;

[0082] FIG. 12 illustrates the variation in the contact resistance between the n+ doped GaN and metal as a function of the operating temperature of the device according to the invention.

DETAILED DESCRIPTION

[0083] FIG. 3 represents a schematic sectional view of a high electron mobility transistor 400 according to an aspect of the invention. In particular, FIG. 3 represents the part of the transistor 400 comprising a source contact 405 and a gate electrode 406. The transistor 400 according to an aspect of the invention comprises a stack of layers comprising a passivation layer 401 and a heterojunction comprising a first semiconductor layer 402 and a second semiconductor layer 403.

[0084] The first semiconductor layer 402 has a gap energy higher than the second semiconductor layer 403. The first semiconductor layer 402 is also called barrier layer or barrier. The second semiconductor layer 403 is also called channel layer or channel. A two-dimensional electron gas or 2 DEG 404 is formed at the interface between the barrier layer 402 and the channel layer 403. The passivation layer 401 is in contact with the first semiconductor layer 402.

[0085] According to an embodiment, the passivation layer 401 is a bilayer comprising the layers 401a and 401b. According to an embodiment, the layers 401a and 401b are made respectively of SiO.sub.2 and SiN.

[0086] The transistor 400 according to an aspect of the invention further comprises the source metal contact 405, a drain metal contact not represented and the gate electrode 406. FIG. 4 represents only the source contact. The gate electrode 406 is positioned between the source and drain metal contacts. According to an embodiment, the gate electrode 406 may have a T shape, with a gate foot in the vicinity of the barrier layer 402.

[0087] In other words, FIG. 4 represents half of the structure of the transistor 400 according to an aspect of the invention, the drain contact not being represented. According to an embodiment of the invention, the transistor 400 is symmetrical with a drain contact identical to the source contact. The gate-drain distance is greater than or equal to the gate-source distance.

[0088] The transistor 400 according to an aspect of the invention further comprises an n+ doped zone 407 being situated inside the heterojunction. In other words, one end 408 of the n+ doped zone 407 is positioned between the source 405 or drain metal contact and the gate foot.

[0089] The n+ doped zone 407 is obtained by ion implantation of an n type dopant.

[0090] According to the embodiment represented in FIG. 4, the barrier layer 402 is made of AlGaN, the channel layer 403 is made of GaN and the n+ doped zone 407 is obtained thanks to a local implantation of silicon with gaussian profile. The ion implantation is associated with an optimised activation annealing, at 975° C. for 10 h, at 1000° C. for 3 hours or at 1050° C. for one hour, to form a n+ doped zone and an efficient contact.

[0091] According to an embodiment, the heterojunction is a III-N type heterostructure based on Al, In or Ga. Examples of such heterostructures are AlGaN/AlN/GaN, AlGaN/GaN, InGaAlN/AlN/GaN, or AlGaN/AlN/AlGaN in which the channel is made of AlGaN.

[0092] According to an embodiment, the heterojunction is a III-N type heterostructure based on ScAlN. Examples of such heterostructures are ScAlN/GaN or ScAlN/AlN/GaN.

[0093] The source or drain metal contact 405 is situated at the level of a recess 409 formed in the stack of layers. The metal contact 405 has a thickness defined by an upper face 405a of the metal contact and a lower face 405b of the metal contact. The two upper and lower faces of the metal contact 405 are substantially parallel to the planes of the layers.

[0094] The upper face 405a is planar so as to reduce parasitic capacitances between the gate electrode 406 and the source or drain metal contact 405. In other words, the thickness of the source or drain contact 405 is constant over the whole region of the contact 406. In an equivalent manner, the thickness of the contact 405 is equal to the thickness of the recess.

[0095] The arrangement of the upper face 405a of the metal contact 405 makes it possible to produce a contact that is very compact, thin and without overflow and thus to reduce to the maximum parasitic capacitances C.sub.pgs between the metal of the contact 405 and the gate metal. The planarization also makes it possible to improve the control of following lithographies.

[0096] The lower face 405b is in contact with the n+ doped implanted zone 407. In other words, the metal contact 405 forms a recess RE with respect to the surface of the barrier layer 402 and the lower face 405b of the contact 405 is below the interface between the first semiconductor layer 402 and the second semiconductor layer 403.

[0097] The recess RE under the barrier layer 402 makes it possible to reduce the metal/semiconductor layer contact resistance R.sub.c to very low values of the order of 50-70 mOhm.Math.mm. This is possible by positioning the ohmic metal on the n+ doped channel zone 407 and not on the barrier layer 402 which has a larger gap. The minimum depth of the recess RE is such that the ohmic metal is deposited on the surface of the n+ doped zone 407 or at the maximum at the depth of the peak of the implantation profile of the n+ doped zone 407.

[0098] The contact 405 further comprises a lateral face 405c substantially normal to the plane of the layers. The distance RET between the lateral face 405c and the end 408 of the n+ doped zone 407 is comprised between 300 nm and 1000 nm. In other words, the metal contact 405 is set back with respect to the end 408 of the n+ doped zone 407.

[0099] The sheet resistance R.sub.sheet associated with the n+ implanted zone 407 is very low and less than 60-90 ohm/sq. This makes it possible to move the metal contact 405 away from the gate electrode 406 without substantially increasing the access resistance. In particular, the n+ layer is at least three times more efficient than the 2 DEG at ambient temperature and five times more efficient at 100° C. The set back RET is sufficiently large to limit parasitic capacitance C.sub.pgs and sufficiently small to avoid increasing the resistance of the n+ layer.

[0100] According to an embodiment, the distance RET is comprised between 300 nm and 1000 nm. The distance RET is here equal to 500 nm.

[0101] The transition resistance R.sub.t between the implanted region and the intrinsic region is low thanks to an optimised ion implantation of Si.

[0102] According to an embodiment, the implantation is mono-energetic of 70 kV/3-5*10.sup.15/cm.sup.2 through a 30 nm surface layer. The use of a multi-energy implantation, normal in wide gap semiconductors, would not give similar results because it would lead to a high resistance R.sub.t.

[0103] The distance L.sub.gs between the end 408 of the n+ doped zone 407 and the gate foot is sufficiently large so as not to degrade the voltage withstand of the gate-source or gate-drain junction. According to an embodiment, L.sub.gs is greater than or equal to 200 nm.

[0104] The Si implantation has a lateral dispersion which does not come too close to the gate foot. L.sub.gs is sufficiently small to limit the contribution of the gas 2 DEG to R.sub.s, for example L.sub.gs is less than 400 nm. According to an embodiment, L.sub.gs is equal to 300 nm.

[0105] According to an embodiment, the metal contact 405 comprises a Ti/Al bilayer with a thickness of the Ti layer comprised between 3 nm and 20 nm and a total thickness equal to 200 nm +/−50 nm.

[0106] FIG. 4 also represents the distribution of the source or drain access resistances: the contact resistance R.sub.c, the resistance of the n+ implanted region R.sub.n+, the transition resistance R.sub.T and the resistance of the two-dimensional electron gas 2 DEG, R.sub.2DEG.

[0107] The access resistance R.sub.s of a source contact of the transistor 400 according to the invention is equal at ambient temperature, T=30° C., to:

R.sub.s=R.sub.c+R.sub.n++R.sub.t+R.sub.2DEG=0.3 Ohm.Math.mm;

At T=150° C.: R.sub.s=R.sub.c+R.sub.n++R.sub.t+R.sub.2DEG=0.35 Ohm.Math.mm

[0108] It may be observed that the access of a transistor 400 according to an aspect of the invention is efficient and very little sensitive to temperature thanks: [0109] to the small length L.sub.gs realisable, of the order of 300 nm; [0110] to the compensation of R.sub.2DEG(T°) by R.sub.t(T°)
The transistor 400 according to an aspect of the invention is obtained by a planar method compatible with manufacture in a CMOS type clean room. The FIG. 5 represents a TEM section of a transistor 400 according to an aspect of the invention. The source contact and the drain contact are both visible in FIG. 5.

[0111] FIG. 6 represents the Si implantation profile as a function of the depth along a direction normal to the plane of the layers. The implantation profile has been obtained for an energy of 70 keV and a dose of 3*10.sup.15/cm.sup.2 through the surface passivation layer 401 formed by a SiO.sub.2/SiN bilayer. The position of the interface of the n+ ohmic contact metal/GaN is represented by the dotted line. The profile has a projected range Rp of 64.5 nm, a sigma dispersion of 23 nm and a lateral extension of 40 nm. The lateral extension represents the lateral overflow of the profile under the mask.

[0112] FIG. 7 schematically represents the method 700 according to an aspect of the invention. The steps of the method 700 according to an aspect of the invention are illustrated in FIGS. 8a to 8p.

[0113] The method 700 according to an aspect of the invention comprises a step 701 of provision of a high electron mobility transistor substrate comprising a stack of layers comprising a passivation layer and a heterojunction comprising a first semiconductor layer and a second semiconductor layer forming a two-dimensional electron gas at the interface thereof. An exemplary high electron mobility transistor substrate used during step 701 is illustrated in FIG. 8a. According to an embodiment, the high electron mobility transistor substrate comprises a Si <111>substrate with high resistivity, a nucleation layer made of AlN, a stress management layer, a buffer layer made of GaN or AlGaN with low Al content, a confinement barrier layer, a channel layer made of GaN and a barrier layer made of AlGaN. According to another embodiment, the high electron mobility transistor substrate comprises a substrate made of Sic or GaN instead of the substrate made of Si. In the case of a GaN substrate, the epitaxy is carried out initially on a GaN wafer.

[0114] In the case of FIG. 8a, the first semiconductor layer is made of AlGaN and the second semiconductor layer is made of GaN. The stack of FIG. 8a further comprises a substrate made of high resistance (HR) Si.

[0115] Step 702 comprises the ion implantation of an n type dopant, illustrated in FIG. 8b. In the example illustrated in FIG. 8b, the implantation is carried out symmetrically in two different zones corresponding to the source contact and to the drain contact.

[0116] According to an embodiment, the ion implantation step 702 is preceded by a photolithography step 702a for the definition of an implantation zone. The photolithography step is known to those skilled in the art.

[0117] According to an embodiment, the dopant is silicon or germanium.

[0118] According to an embodiment, step 702 comprises a mono-energy implantation of Si ions of 70 kV/3-5*10.sup.15/cm.sup.2 through a 30 nm surface layer. An implantation profile according to the invention is described in FIG. 6. The use of a multi-energy implantation, normal in large gap semiconductors for generating doped wells, is not the most suitable because it leads to a high transition resistance R.sub.t.

[0119] The method 700 further comprises a step 703 of annealing of the dopant. According to one embodiment, the dopant is Si and the annealing may be carried out at 975° C. for 10 hours, at 1000° C. for three hours or at 1050° C. for one hour.

[0120] A long annealing at low temperature makes it possible to avoid the plastic deformation of the GaN/Si wafers.

[0121] Si is an n+ dopant very suited to the production of a localised n+ doped zone: [0122] It is activable at low temperature in III-N compounds such as AlN, AlGaN or GaN; [0123] It has a solubility greater than 4*10.sup.20/cm.sup.3 enabling very high doping, for example greater than 10.sup.20/cm.sup.3, and negligible diffusion; [0124] It is an element compatible with CMOS and planar technologies.

[0125] According to an embodiment, the annealing step 703 is preceded by the removal of the resin used for the lithography step. Step 703 of removal of the resin and annealing of the dopant is illustrated in FIG. 8c.

[0126] The method 700 according to an embodiment of the invention further comprises a step 704 of deposition of a dielectric layer in contact with the passivation layer. Step 704 of deposition of a dielectric layer is illustrated in FIG. 8d.

[0127] The method 700 comprises a step of etching 705 of the stack of layers and the dielectric layer to form a recess directly in line and in contact with the implanted zone, the recess being intended to accommodate a source or drain metal contact, the distance separating one end of the implanted zone and a lateral wall of the recess being comprised between 300 nm and 1000 nm, the lower face of the recess being situated below the interface between the first and the second semiconductor layer. According to an embodiment, the etching step 705 comprises a photolithography step 705a to define the region to etch.

[0128] The step 705 of photolithography and etching of the stack is illustrated in FIG. 8e.

[0129] According to an embodiment, the etching carried out during step 705 is a dry etching.

[0130] According to an embodiment, the etching step 705 also comprises the removal of the resin used during the photolithography sub-step. The stack of layers obtained after the removal of the resin is illustrated in FIG. 8f.

[0131] The method 700 according to an aspect of the invention further comprises a step 706 of deposition of a metal layer intended to form the source or drain contact followed by a step 707 of chemical mechanical polishing of the metal layer to obtain a planarized upper surface of the source or drain metal contact.

[0132] Step 706 is also illustrated in FIG. 8g. The result of step 707 of chemical mechanical polishing of the metal layer is illustrated in FIG. 8h. According to an embodiment, step 706 comprises the deposition of a Ti/Al bimetal layer with a thickness of the Ti layer comprised between 3 nm and 20 nm and a total thickness equal to 200 nm +/−50 nm.

[0133] According to an embodiment, step 707 further comprises a sub-step 707b of annealing of the metal. At the end of step 707, a metal contact having a planarized surface is obtained.

[0134] Step 707 makes it possible to reduce the parasitic capacitance between the metal of the contact and the gate electrode and to optimise the following lithography.

[0135] The method 700 further comprises a step 708 of definition and deposition of a gate electrode.

[0136] According to an embodiment, step 708 further comprises the sub-steps: [0137] 708a of deposition of a dielectric layer; step 708a is illustrated in FIG. 8i; [0138] 708b of photolithography to define the gate foot; step 708b comprising the deposition of a resin layer is illustrated in FIG. 8j; [0139] 708c of etching of the gate foot and removal of the resin used during the photolithography step 708b to define the gate foot; step 708c is illustrated in FIG. 8k; [0140] 708d of deposition of a metal used for the gate electrode; step 708d is illustrated in FIG. 8l; [0141] 708e of polishing of the metal used for the gate foot; step 708e is illustrated in FIG. 8m; [0142] 708f of deposition of a metal layer intended to form the gate head; step 708f is illustrated in FIG. 8n; [0143] 708g of photolithography to define the gate head; step 708g is illustrated in FIG. 8o; [0144] 708h of etching of excess gate head metal and removal of the resin used to define the gate head; step 708g is illustrated in FIG. 8p.

[0145] The method 700 according to an aspect of the invention is robust because it enables alignment tolerances between the ohmic contact metal, the n+ doped zone and the gate head thanks to planar technology. In addition, thanks to ion implantation technology, the method 700 according to the invention is precise, uniform and reproducible.

[0146] According to an embodiment of the method 700, it is possible to produce the drain access in addition to the source access. If the method 700 according to an aspect of the invention is used only for the source access, the drain access is produced without a step of implantation of Si. In other words, the implantation of Si is masked in correspondence with the drain contact and the drain contact is of “full recess” type.

[0147] FIGS. 9 to 12 illustrate the variation in the different terms contributing to the access resistance of the device as a function of its operating temperature. FIG. 9 shows that the overall contact resistance Rc+Rn.sub.++Rt decreases with the operating temperature. It goes from 0.2 ohm.Math.mm to 0.11 ohm.Math.mm between 30° C. and 150° C., which is very favourable for the source or drain resistance of the transistor.

[0148] This behaviour is due to the significant decrease, from 0.11 to 0.024 Ohm.Math.mm, of the transition resistance Rt with temperature, illustrated in FIG. 10, whereas the resistance of the n+ doped zone only increases by 3%, as is shown in FIG. 11 and that the metal/n+ contact resistance remains constant and equal to around 47 mOhm.Math.mm, as shown in FIG. 12.

[0149] The source or drain resistance of the transistor according to an aspect of the invention varies very little with temperature, which makes the transistor 400 according to the invention particularly suited for high frequency power applications.

[0150] It will be appreciated that the various embodiments described previously are combinable according to any technically permissible combinations.