A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional 2D semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as metal fin structure, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional 2D semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as metal fin structure, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

A high electron mobility transistor (HEMT) includes a substrate, and a channel layer over the substrate, wherein and at least one of the channel layer or the active layer comprises indium. The HEMT further includes an active layer over the channel layer. The active layer has a band gap discontinuity with the channel layer.

Ohmic contacts, including materials and processes for forming n-type ohmic contacts on n-type semiconductor substrates at low temperatures, are disclosed. Materials include reactant layers, n-type dopant layers, capping layers, and in some instances, adhesion layers. The capping layers can include metal layers and diffusion barrier layers. Ohmic contacts can be formed on n-type semiconductor substrates at temperatures between 150 and 250 C., and can resist degradation during operation.

The present invention describes a microelectronic sensor based on the combination of an open-gate pseudo-conductive high-electron mobility transistor and a metamaterial electrode installed in the open gate area of the transistor and operated in the sub-THz and THz frequency range. The sensor can be used in different applications, for example, chemical sensing and biomolecular diagnostics, monitoring glucose levels in blood and biometric authentication of a user.

A method for forming a III-nitride semiconductor device involves determining work functions of a first III-nitride contact layer and a first metal contact. The determined work function of the first III-nitride contact layer is based on a group III element of the first III-nitride contact layer. Based on the determined work functions of the first III-nitride contact layer and of the first metal contact, it is determined that the work function of the first III-nitride contact layer should be adjusted. The III-nitride semiconductor device is formed including the first III-nitride contact layer adjacent to a second III-nitride contact layer, the first metal contact arranged on the first III-nitride contact layer, and a second metal contact arranged on the second III-nitride contact layer. The first III-nitride contact layer of the formed III-nitride semiconductor device is a boron nitride alloy having an amount of boron that adjusts the work function of the first III-nitride contact layer relative to the determined work function of the first metal layer based on the group III element of the first III-nitride contact layer.

A CMOS process is disclosed for manufacturing an integrated circuit including both MOSFETS and GaN HEMT devices. Each GaN HEMT device resides within an oxidized window that exposes a silicon substrate having a <111> crystal lattice orientation.

Provided herein is: a SiC substrate having a front surface on which a GaN layer is stacked; a source electrode formed on a front surface of the GaN layer; a MIM capacitor formed on a front surface of the source electrode; and a via hole extending from a rear surface of the SiC substrate to reach the source electrode; wherein a barrier metal layer is included in the source electrode, and wherein the depth end of the via hole is placed between a rear surface of the source electrode and a rear surface of the barrier metal layer. Accordingly, intrusion of a halogen element, in particular, Br, into an insulating film that is placed in the MIM capacitor, is suppressed over a long term.

A nanowire system includes a substrate and at least one nanowire structure which extends out along an axis from a surface of the substrate. The nanowire structure comprises a light emitting diode and a device driver electrically coupled to control an operational state of the light emitting diode. The light emitting diode and the device driver are integrated to each share at least one doped region.