A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.

A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover the gate stack; forming an opening in the interlayer dielectric to expose to the gate stack; forming a glue layer over the interlayer dielectric and in the opening; partially removing the glue layer, in which a portion of the glue layer remain in the opening; and tuning a profile of the remained portion of the glue layer.

Devices, transistor structures, systems, and techniques, are described herein related to selective gate oxide formation on 2D materials for transistor devices. A transistor structure includes a gate dielectric structure on a 2D semiconductor material layer, and source and drain structures in contact with the gate dielectric structure and on the 2D semiconductor material layer. The source and drain structures include a metal material or metal nitride material and the gate dielectric structure includes an oxide of the metal material or metal nitride material.

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional 2D semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as metal fin structure, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

An object of the present invention is to provide an organic thin film transistor that has an organic semiconductor film manufactured by using a compound having excellent solubility to an organic solvent and that has excellent carrier mobility, a novel compound, an organic thin film transistor material, an organic semiconductor film, an organic thin film transistor composition, and a method of manufacturing an organic thin film transistor using this. The organic thin film transistor according to the present invention has an organic semiconductor film containing a compound represented by Formula (1). ##STR00001##

A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover the gate stack; forming an opening in the interlayer dielectric to expose to the gate stack; forming a glue layer over the interlayer dielectric and in the opening; partially removing the glue layer, in which a portion of the glue layer remain in the opening; and tuning a profile of the remained portion of the glue layer.

Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional 2D semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as metal fin structure, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

A nitride high electron mobility transistor having a strain balance of an aluminum gallium nitride insertion layer is described. The transistor sequentially includes: a substrate and a GaN buffer layer located on the substrate; an AlyGa1-yN insertion layer located on the GaN buffer layer; an AlxGa1-xN barrier layer located on the AlyGa1-yN insertion layer opposite to the GaN buffer layer; a GaN cap layer located on the AlxGa1-xN barrier layer; a -shaped source electrode and drain electrode provided in recesses formed by the removal of the GaN cap layer and some thickness of the AlxGa1-xN barrier layer; and a gate electrode located between the source electrode and the drain electrode. An AlzGa1-zN insertion layer may be further included between the AlxGa1-xN barrier layer and the GaN cap layer.