A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

An anti-fuse device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a salicide layer formed on a first portion of the gate electrode such that a second portion of the gate electrode omits the salicide layer, wherein a hard breakdown of at least a portion of the gate insulating film at a time of programming the anti-fuse device.

A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure recess; performing an ion implantation on the work function layer; and forming a gate layer on the work function layer after the ion implantation.

A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and within 100 μm at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of metal same with a metal contained in the lower layer of the lower electrode.

Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer.