A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

A semiconductor device includes a semiconductor substrate, a memory gate, and a data storage element. The semiconductor substrate includes a memory well which has two source/drain regions and a channel region between the source/drain regions. The memory gate is disposed above the channel region. The data storage element includes a ferroelectric material, and is disposed around the memory gate to separate the memory gate from the channel region.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

A ferroelectric semiconductor device of the present disclosure includes a substrate having a channel structure, a trench pattern having a bottom surface and a sidewall surface in the channel structure, a dielectric layer disposed on the bottom surface and the sidewall surface of the trench pattern, and a gate electrode layer disposed on the dielectric layer. The dielectric layer includes a ferroelectric layer pattern and a non-ferroelectric layer pattern that are disposed along the sidewall surface of the trench pattern.

A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.

A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

A transistor device and the manufacturing methods are described. The device includes a gate structure having a gate layer and a ferroelectric layer, source and drain terminals, and a crystalline channel portion. The source and drain terminals are disposed at opposite sides of the gate structure. The crystalline channel portion extends between the source and drain terminals. The source and drain terminals are disposed on the crystalline channel portion and the gate structure is disposed on the crystalline channel portion. The crystalline channel portion includes a first material containing a Group III element and a Group V element, the gate layer includes a second material containing a Group III element and a rare-earth element, and the ferroelectric layer includes a third material containing a Group III element, a rare-earth element and a Group V element.

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.