There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device comprising, a first active pattern on a substrate, the first active pattern including a first lower pattern, which extends in a first direction, and first sheet patterns, which are on the first lower pattern, a second active pattern on the substrate, the second active pattern including a second lower pattern, which is spaced apart from the first lower pattern in a second direction and a second sheet patterns, which are on the second lower pattern, wherein the first lower pattern and the second lower pattern is separated by a fin trench.

A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode; a first gate electrode that is disposed to surround the drain electrode in a plan view and performs a normally-on operation; and a second gate electrode is disposed to surround the first gate electrode in a plan view and performs a normally-off operation. The first gate electrode and the second gate electrode include straight portions in which both an edge of the first gate electrode and an edge of the second gate electrode are substantially straight in the plan view and end portions formed by corner portions which are curved or bent in the plan view. An interval, a length, or a radius of curvature of one of the first gate electrode, the second gate electrode, and the source electrode is set such that concentration of an electric field at the end portion is alleviated.

A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.

A high-k metal gate device and manufacturing method thereof are provided in the present invention. The method uses a silicon material layer as a battier layer for the lower silicon nitride layer in the NMOS region and then performs an annealing process to turn the silicon material layer into a TiSiN interlayer of the PMOS region and a TiSiN layer of the NMOS region, respectively. TiSiN material can prevent subsequent upper metal atoms from diffusing downward and improve the stability of the metal gate device. Additionally, the silicon material remained on the surface of the NMOS region is subsequently removed, thereby eliminating differences of the thickness of the residual silicon material layer and fluctuations of the threshold voltage of the NMOS region resulted from the differences thereof and further improving the stability of the NMOS device.

A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

A semiconductor device according to an embodiment includes a silicon carbide layer, a silicon oxide layer including carbon, the silicon oxide layer including single bonds between carbon atoms which are at least a part of the carbon, the number of the single bonds between carbon atoms being greater than the number of double bonds between carbon atoms which are at least a part of the carbon, and a region provided between the silicon carbide layer and the silicon oxide layer, the region including at least one element from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), scandium (Sc), yttrium (Y), and lanthanoids (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu).

Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.