A method of detecting atomic scale defects in semiconductors, comprising the steps of scanning the surface of the semiconductor with a field emission scanning electron microscope (SEM) to form an SEM image thereof; scanning the SEM image with a light detector and monochromator to obtain a cathodoluminescence (CL) spatial intensity map of the SEM image; determining the CL spectra, i.e. the CL intensity against photon energy for each integral CL intensity; and comparing the CL intensity to a threshold, whereby those semiconductors whose CL intensity is above the threshold are deemed to be defective

A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

A graphene nanoribbon precursor has a structure that is indicated by a predetermined chemical formula. In the chemical formula (1), n.sub.1 is an integer that is greater than or equal to 1 and less than or equal to 6; X, Y, and Z are F, Cl, Br, I, H, OH, SH, SO.sub.2H, SO.sub.3H, SO.sub.2NH.sub.2, PO.sub.3H.sub.2, NO, NO.sub.2, NH.sub.2, CH.sub.3, CHO, COCH.sub.3, COOH, CONH.sub.2, COCl, CN, CF.sub.3, CCl.sub.3, CBr.sub.3, or CI.sub.3; and when desorption temperatures of X, Y and Z from carbon atoms constituting six-membered rings are respectively T.sub.X, T.sub.Y, and T.sub.Z, a relationship of T.sub.X<T.sub.YT.sub.Z is satisfied.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

A Schottky barrier diode includes a graphene nanoribbon, a first electrode connected to one end of the graphene nanoribbon, and a second electrode connected to the other end of the graphene nanoribbon. The graphene nanoribbon includes a first part and a second part which are connected in the length direction of the graphene nanoribbon and which differ in electronic state. For example, edges of the first part in a length direction of the graphene nanoribbon are terminated with a first modifying group and edges of the second part in the length direction of the graphene nanoribbon are terminated with a second modifying group.

A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.

A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500? C. and 2600? C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.

Hot metal dissolution of carbon atoms is used to structure a diamond substrate. A layer of catalytic material is deposited on at least a portion of a surface of the diamond substrate. The layer of catalytic material may be structured using photolithography to define a gap exposing the surface of the diamond substrate, where the gap has a (110) orientation relative to the crystal structure of the diamond substrate. The exposed surface of the diamond substrate is etched to form at least one recess having at least one (111) oriented diamond surface (facet). The catalytic material is removed by a suitable cleaning process. The (111) oriented surface is then overgrown with diamond comprising a dopant resulting in a conductivity of the overgrown diamond that is different from the conductivity of the doped substrate. The doping concentration of the overgrown diamond is greater than 10.sup.19 cm.sup.3.

A multilayer graphene, a method of forming the same, a device including the multilayer graphene, and a method of manufacturing the device are provided. In the method of forming the multilayer graphene, a first graphene is formed on an underlayer, and then a multilayer graphene is formed by exposing two adjacent areas on the first graphene to a source gas. By differentiating temperatures and source gasses, the multilayer graphene has different electrical characteristics in the two adjacent areas.