A semiconductor device includes a substrate, a drift layer provided on an upper surface side of the substrate, a base layer provided on the upper surface side of the drift layer, an upper semiconductor layer provided on the upper surface side of the base layer, a first electrode provided on the upper surface of the substrate, a second electrode provided on a rear surface of the substrate, a trench extending to the drift layer from the upper surface of the substrate and a gate electrode provided inside the trench, wherein an inner side surface of the trench has a first surface and a second surface provided below the first surface, the second surface tilts inward of the trench with respect to the first surface, and an intersection point of the first surface and the second surface is provided below the base layer.

A field effect transistor includes a substrate, a material layer on a surface of the substrate and including a two-dimensional material or carbon nanotubes, and particles interposed between the substrate and the material layer.

The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region. The first and second two-dimensional metallic contacts contact sideways the channel region to form lateral semiconductor-metallic junctions.

There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n−1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.

The present disclosure provides a reference electrode for providing a reference potential during measurement of a property of a sample. The reference electrode comprising: a reference electrode layer; and a reference layer provided over at least a part of the reference electrode layer and defining a sample receiving region which is separated from the reference electrode layer by the reference layer. In one embodiment, the reference layer comprises fluorinated or silanized graphene and/or fluorinated or silanized graphene oxide. Alternatively, the graphene or graphene oxide are functionalised or doped so as to form a super-hydrophobic reference layer.

A sensing assembly comprises for detecting a property of a sample comprises a field effect transistor (FET) configured to output a first signal indicative of a property of a sample comprises: a first layer providing a sensing surface; a channel provided below the first layer; and a drain and a source in electrical communication with the channel. The sensing assembly may further comprise a gate provided below the first layer and the first layer comprises a one-dimensional or two-dimensional material. Alternatively or additionally, the first layer comprises N-polar hexagonal boron nitride (hBN).

The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

A field effect transistor (FET), a method of fabricating the field effect transistor, and an electronic device are provided. The field effect transistor comprises: a source and a drain, the source being made of a Dirac material (103); a channel disposed between the source and the drain, and doped opposite to the source; and a gate (106) disposed on the channel and electrically insulated from the channel.