By widening a terrace on a crystal surface on a bottom face of a recess by step flow caused by heating, a flat face is formed on the bottom face of the recess, a two-dimensional material layer made of a two-dimensional material is formed on the formed flat face, and then a device made of the two-dimensional material layer is produced.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.

The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.

A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire.

A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.010.sup.22 cm.sup.3 or more, a SiO.sub.2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO.sub.2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO.sub.2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO.sub.2 layer and that has a carbon density of 1.010.sup.19 cm.sup.3 or less.

A method and apparatus, the method comprising: forming a layer of two dimensional material (23), in particular graphene, on a first release layer; forming, possibly a (gate) insulating layer (35), and at least two, preferably three, electrodes (25); forming a second release layer overlaying at least a portion of the layer of two dimensional material; providing a mouldable polymer (24, 26, 28) overlaying the at least two electrodes and the second release layer; and removing the first and second release layers to provide a cavity (29) between the mouldable polymer (26) and the layer of two dimensional material (23).

A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

A laminated body of an embodiment includes: a silicon layer; a first beryllium oxide layer on the silicon layer; and a diamond semiconductor layer on the first beryllium oxide layer.