A complementary transistor is constituted of a first transistor TR.sub.1 and a second transistor TR.sub.2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 20.sub.1, 20.sub.2 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 21.sub.1, 21.sub.2 respectively.

A device comprising: at least one first layer, such as a graphene layer, at least one second layer of transition metal dichalcogenide, wherein the at least one first layer and the at least one second layer of transition metal dichalcogenide form at least one heterojunction. The first and second layers are laterally displaced but may overlap over a length of 0 nm to 500 nm. A low-resistance contact is formed. The device can be a transistor including a field effect transistor. The layers can be formed by chemical vapor deposition. The graphene can be heavily p-doped. Transistor performance data are described.

A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

The present disclosure provides a manufacturing method of a thin film transistor, including: selecting a substrate, and forming a bottom gate, a gate insulating layer and a source-drain above the selected substrate, wherein the bottom gate and the source-drain adopts a conductive metal oxide with an adjustable work function as a metal conducting electrode; rinsing and drying the source-drain of the selected substrate, and ozone cleaning dried source-drain for a predetermined time under a predetermined illumination condition, bombarding the source-drain with oxygen plasma for a period of time, forming an active layer made of a carbon material over the source-drain; forming a passivation layer over the active layer. The implementation of the disclosure can reduce the contact resistance and improve the performance of the carbon-based thin film transistor device by adjusting the work function of the contact surface between the conductive metal and the active layer.

A semiconductor device includes a substrate, a first dielectric layer on the substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, an ILD layer overlying the trench, an nFET disposed over the trench, and a pFET disposed over the trench and spaced apart from the nFET.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

Disclosed herein is a composite transistor which includes a first transistor TR.sub.1 including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor TR.sub.2 including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.

A switchable array micro-lattice comprises a plurality of interconnected units wherein the units are formed of graphene tubes. JFET gates are provided in selected members of the micro-lattice. Gate connectors are routed from an external surface of an integrated circuit (IC) through openings in the micro-lattice to permit control of the JFET gates.

Production of a transistor, the channel structure of which comprises at least one finned channel structure, the method comprising: forming, from a substrate (1), a molding block (3), forming, on the molding block, a thin layer (7) made from a given semiconductor or semi-metallic material, and consisting of one to ten atomic or molecular monolayers of two-dimensional crystal, withdrawing the molding block while retaining a portion (7a) of the thin layer extending against a lateral face of the molding block, said retained portion (7a) forming a fin that is capable of forming a channel structure of the transistor, producing a coating gate electrode against said fin.

The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.