Field effect transistors (FET) including quantum layers. A FET may include a substrate, and an oxide layer disposed over the substrate. The oxide layer may include a first section and a second section positioned adjacent the first section. The FET may also include a first quantum layer disposed over the first section of the oxide layer, and a second quantum layer disposed over the second section of the oxide layer, and a first segment of the first quantum layer. Additionally, the FET may include a drain region disposed directly over a second segment the first quantum layer. The second segment of the first quantum layer may be positioned adjacent the first segment of the first quantum layer. The FET may further include a source region disposed over the second quantum layer, and a channel region formed over the second quantum layer, between the drain region and the source region.

A method for manufacturing a biological field-effect transistor (BioFET) is disclosed. In some implementations, the method may include preparing a carbonaceous dispersion by adding a three-dimensional (3D) graphene into a solvent; depositing the carbonaceous dispersion onto a p-type silicon wafer; spin-coating a positive photoresist over the carbonaceous dispersion; forming source and drain terminals on the p-type silicon wafer, the source and drain terminals in contact with the 3D graphene of the carbonaceous dispersion; removing residual photoresist from the carbonaceous dispersion by placing the p-type silicon wafer in 1-methyl-2-pyrrolidone (NMP); and biofunctionalizing the carbonaceous dispersion with a molecular recognition element configured to alter one or more electrical properties of the Bio-FET in response to exposure of the molecular recognition element to the analyte.

Semiconductor devices having improved electrical characteristics are described, as are methods of fabricating the same. The semiconductor device may include a first gate electrode on a substrate and extending in a first direction, a second gate electrode on the substrate and running across the first gate electrode while extending in a second direction, and a channel structure between the second gate electrode and lateral surfaces in the second direction of the first gate electrode and between the second gate electrode and a top surface of the first gate electrode. The channel structure may include a first dielectric layer that covers in contact with the lateral surfaces and the top surface of the first gate electrode; a second dielectric layer on the first dielectric layer and in contact with the second gate electrode; and a channel layer between the first dielectric layer and the second dielectric layer.

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm.sup.2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

The present invention relates to a method of forming a material on a graphene layer structure 5 for injecting charge into, or extracting charge out of, the graphene layer structure 5, the method comprising: providing a graphene layer structure 5 having one or more first portions 25 on a non-metallic substrate 10, said one or more first portions 25 having one or more surface defects comprising excess out-of-plane material 15; plasma etching the one or more first portions 25 of the graphene layer structure 5 to remove the out-of-plane material 15; depositing a material 30 for injecting charge into, or extracting charge out of, the graphene layer structure 5 onto the one or more plasma-etched first portions 25.

A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The substrate includes a plurality of protrusions spaced apart from each other, and one of the plurality of graphene nanoribbons is on the substrate and between two adjacent protrusions. An interdigital electrode is placed on the graphene nanoribbon composite structure, and the interdigital electrode covers the plurality of protrusions and is electrically connected to the plurality of graphene nanoribbons.

A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.

A method for using a graphene field-effect transistor (GFET) as a reconfigurable circuit, the method comprising the following steps: depositing a liquid dielectric over a graphene channel of the GFET; applying an activation energy via a first electric field across the liquid dielectric and the graphene channel to electrochemically produce chemical species within the liquid dielectric such that the chemical species accumulate at, and molecularly bond with, the graphene channel thereby decreasing a conductivity of the graphene channel; and applying a deactivation energy via a second electric field of opposite polarity to the first electric field to remove interaction between the chemical species and the graphene channel to increase the conductivity of the graphene channel.

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.