A method of manufacturing a semiconductor device includes forming a profile of net doping in a drift zone of a semiconductor body by multiple irradiations with protons and generating hydrogen-related donors by annealing the semiconductor body. At least 50% of a vertical extension of the drift zone between first and second sides of the semiconductor body is undulated and includes multiple doping peak values between 110.sup.13 cm.sup.3 and 510.sup.14 cm.sup.3.

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15? and 0.65?. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

A photoresist is applied to a front surface of a semiconductor wafer rotating at a predetermined rotational speed and a photoresist film having a predetermined thickness is formed and dried. Next, a chemical is dripped while the semiconductor wafer is rotated at the predetermined rotational speed or less, whereby an edge part of the photoresist film is dissolved and removed by the chemical while the predetermined thickness of the photoresist film is maintained. A predetermined pattern is transferred to the photoresist film by exposure and development. After the development, without performing UV curing or post-bake, the photoresist film is used as a mask and helium irradiation having a range of 8 m or greater from the front surface of the semiconductor wafer is performed. Thus, a predetermined impurity may be implanted with good positioning accuracy in a predetermined region, using the photoresist film as a mask and cost may be reduced.

A chip resistor includes: a board having a device formation surface, a back surface opposite from the device formation surface and side surfaces connecting the device formation surface to the back surface, a resistor portion provided on the device formation surface, a first connection electrode and a second connection electrode provided on the device formation surface and electrically connected to the resistor portion, and a resin film covering the device formation surface with the first connection electrode and the second connection electrode being exposed therefrom. Intersection portions of the board along which the back surface intersects the side surfaces each have a rounded shape.

A semiconductor element capable of adjusting a barrier height .sub.Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the change of the barrier height caused by the bias described above up to a deep degeneration range. An electron Fermi level (E.sub.F) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

A semiconductor system including a planar anode contact, a planar cathode contact, and a volume of n-conductive semiconductor material, which has an anode-side end and a cathode-side end and extends between the anode contact and the cathode contact. A p-conductive area extends from the anode-side end of the volume toward the cathode-side end of the volume without reaching the cathode-side end. The p-conductive area has two sub-areas which are separated from one another in a cross section lying transversely with respect to the anode contact and the cathode contact, which delimit a sub-volume of the volume filled with n-conductive semiconductor material. The sub-volume is open toward the cathode contact, and is delimited by cathode-side ends of the sub-areas. A distance of the two sub-areas defining the opening is smaller than a distance between the two sub-areas prevailing outside of the opening and lying between anode side ends of the sub-areas.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.