A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10.sup.17 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10.sup.17 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

Provided is a semiconductor device in which a lifetime control region including a lifetime killer is provided, below a base region, from at least a part of a transistor portion to a diode portion, the transistor portion includes: a main region spaced apart from the diode portion in a top view; a boundary region located between the main region and the diode portion and overlapping the lifetime control region in a top view; and a plurality of gate trench portions provided from an upper surface of the semiconductor substrate to a drift region through the base region, the plurality of gate trench portions include: a first gate trench portion provided in the main region; and a second gate trench portion provided in the boundary region, and a signal transmission timing of the first gate trench portion is different from a signal transmission timing of the second gate trench portion.

A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*10.sup.15 cm.sup.−3 for at least 5% of the total extension of the transition region in the extension direction.

Techniques are provided herein to form a semiconductor diode device within an integrated circuit. In an example, a diode device includes separate fins or bodies of semiconductor material that are separated by an insulating barrier. One of the fins or bodies is doped with n-type dopants while the other fin or body is doped with p-type dopants. Each of the first and second fins or bodies includes an epitaxially grown region over it that includes the corresponding dopant type with a higher dopant concentration. Additionally, each of the first and second fins or bodies includes another epitaxially grown region on the backside (e.g., under the fins or bodies) of the corresponding dopant type with a lower dopant concentration compared to the epitaxial regions on the opposite side of the fins or bodies. An undoped or lightly doped layer may also be formed between the epitaxially grown regions on the backside.