A device includes a first doped semiconductor region and a second oppositely doped semiconductor region that are separated by an undoped or lightly-doped semiconductor drift region. The device further includes a first electrode structure making an ohmic contact with the first doped semiconductor region, and a second electrode structure making a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows flow of both electrons and holes into, and out of, the device.

A semiconductor element capable of adjusting a barrier height ϕ.sub.Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (E.sub.F) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.

A device includes a substrate having a top surface and a bottom surface. A first doping well having a first part and a second part is located in the substrate. An undoped moat is in the substrate between the first doping well and a second doping well. A diode includes an anode with an increased first doping concentration region in the first doping well and a cathode with an increased second doping concentration region in the second doping well. An isolation region is in the first doping well having a first portion proximate the top surface and a second portion distal to the top surface. A gap made of an undoped region is in the first doping well between the first part and the second part. The gap is located between the distal portion of the isolation region and the bottom surface of the substrate.

It is an object to provide technology enabling reduction in variation of an oxygen concentration among silicon wafers. A semiconductor device manufacturing method includes: a first step of introducing oxygen to increase an oxygen concentration of a silicon wafer when the oxygen concentration of the silicon wafer is lower than a predetermined threshold, and deriving oxygen to decrease the oxygen concentration of the silicon wafer when the oxygen concentration of the silicon wafer is higher than the threshold; a second step of forming a first surface structure; a third step of grinding the silicon wafer from a second surface; and a fourth step of forming a second surface structure.

A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

A PIN diode includes a first polycrystalline silicon region doped with a P-type of conductivity, a second polycrystalline silicon region doped with an N-type of conductivity and an intrinsic polycrystalline silicon region. At least the intrinsic polycrystalline silicon region is configured to include fluorine atoms. A polycrystalline silicon bar may include the first polycrystalline silicon region, the second polycrystalline silicon region and the intrinsic polycrystalline silicon region. The polycrystalline silicon bar may be supported by an insulating region within a semiconductor substrate.

The present invention is related to a substrate (10) for a controlled implantation of ions (80) into a bulk (20), the substrate (10) comprising the bulk (20) composed of a crystalline first material (70), the bulk (20) comprising an implantation region (28) and a surface (22), wherein the implantation region (28) is located within the bulk (20) and along an implantation direction (82) at an implantation depth (26) below an implantation area (24) on the surface (10) of the bulk (20). Further, the present invention is related to a method of preparing a substrate (10) for a controlled implantation of ions (80) into a bulk (20), preferably the aforementioned substrate (10), the substrate (10) comprising the bulk (20) composed of a crystalline first material (70), the bulk (20) comprising an implantation region (28) and the surface (22), wherein the implantation region (28) is located within the bulk (20) and along an implantation direction (82) at an implantation depth (26) below an implantation area (24) on the surface (22) of the bulk (20).

Electronic devices and more particularly diamond-based electronic devices and corresponding contact structures are disclosed. Electrical contact structures to diamond layers, including n-type, phosphorus doped single-crystal diamond are disclosed. In particular, electrical contact structures are formed through an arrangement of one or more nanostructured carbon layers with high nitrogen incorporation that are provided between metal contacts and n-type diamond layers in diamond-based electronic devices. Nanostructured carbon layers may be configured to mitigate reduced phosphorus incorporation in n-type diamond layers, thereby providing low specific contact resistances for corresponding devices. Diamond p-i-n diodes for direct electron emission applications are also disclosed that include electrical contact structures with nanostructured carbon layers.

A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.