A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

Embodiments of the disclosure provide a bandgap reference circuit, including: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region.

A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

Embodiments of the disclosure provide a bandgap reference circuit, including: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region.

The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

Metal-oxide-polysilicon tunable resistors and methods of fabricating metal-oxide-polysilicon tunable resistors are described. In an example, a tunable resistor includes a polysilicon resistor structure disposed above a substrate. A gate oxide layer is disposed on the polysilicon resistor structure. A metal gate layer is disposed on the gate oxide layer.