A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material.

A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.

A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a first contact coupled to the hyper-abrupt junction region and a second contact coupled to the substrate to define a varactor. The first and second superlattices may each include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

A method for making semiconductor device may include forming a hyper-abrupt junction region on a substrate and including a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The method may further include forming a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.

A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a first contact coupled to the hyper-abrupt junction region and a second contact coupled to the substrate to define a varactor. The first and second superlattices may each include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.