A metal oxide semiconductor (MOS) varactor includes a first diffusion region of a first polarity and a second diffusion region of the first polarity on a semiconductor substrate. The MOS varactor further includes a channel between the first diffusion region and the second diffusion region on the semiconductor substrate. The channel has a surface dopant concentration less than 4e10.sup.17.

A variable capacitor includes a mesa on a substrate. The mesa has multiple III-V semiconductor layers and includes a first side and a second side opposite the first side. The first side has a first sloped portion and a first horizontal portion. The second side has a second sloped portion and a second horizontal portion. A control terminal is on a third side of the mesa. A first terminal is on the first side of the mesa. The first terminal is disposed on the first horizontal portion and the first sloped portion. A second terminal is also on the substrate.

An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

Fabricating a semiconductor device includes receiving a substrate structure including a substrate. The substrate structure further includes a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate. The substrate structure further includes a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion. A mask is applied to the portion of the bottom spacer formed on the first bottom source/drain. The portion of the bottom spacer formed on the second bottom source/drain of the varactor portion is removed. The mask is removed from the portion of the bottom spacer formed on the first bottom source/drain. A gate oxide is deposited on the vertical transistor portion and the varactor portion.

A capacitor structure including a silicon material layer, a support frame layer, and a capacitor is provided. The support frame layer is disposed in the silicon material layer. The support frame layer has recesses. There is a cavity between two adjacent recesses. The support frame layer is located between the cavity and the recess. The support frame layer has a through hole directly above the cavity. The capacitor is disposed in the silicon material layer. The capacitor includes a first insulating layer and a first electrode layer. The first insulating layer is disposed on the support frame layer. The first electrode layer is disposed on the first insulating layer and fills the recess and the cavity.

A structure for improved noise signal isolation in semiconductor devices. In one embodiment, the structure includes a second-conductivity type substrate, a 1.sup.st first-conductivity type well, a 1.sup.st first-conductivity type layer, a second-conductivity type layer positioned between the 1.sup.st first-conductivity type well and the 1.sup.st first-conductivity type layer. The structure also includes a 2.sup.nd first-conductivity type well, and a 2.sup.nd first-conductivity type layer positioned between the 2.sup.nd first-conductivity type well and the 1.sup.st first-conductivity type layer. The 1.sup.st first-conductivity type layer and the second-conductivity type layer are positioned between the P type substrate and the 1.sup.st first-conductivity type well, and the 1.sup.st first-conductivity type well is laterally separated from the 2.sup.nd first-conductivity type well.

Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.

A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.

An apparatus is provided that includes a substrate. In addition, the apparatus includes a first electrically conductive path arranged in a second layer above the substrate and forming a first connection of the apparatus, and a second electrically conductive pad arranged in the second layer and forming a second connection of the apparatus. An electrically conductive element is arranged in a first layer spaced apart from the second layer. The electrically conductive element forms a first capacitor with either the first pad or the second pad. In addition, a first coil is arranged in the first layer, the second layer, or in both layers. A first end of the first coil is connected to the second pad.

A metal oxide semiconductor (MOS) varactor includes a first diffusion region of a first polarity and a second diffusion region of the first polarity on a semiconductor substrate. The MOS varactor further includes a channel between the first diffusion region and the second diffusion region on the semiconductor substrate. The channel has a surface dopant concentration less than 4 e10.sup.17.