A metal-oxide-semiconductor (MOS) capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a first terminal connected with the surface of the substrate, and a second terminal connected with the conductive layer. The oxide layer can be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. Each of the first terminal and the second terminal can be exposed along the surface of the substrate for surface mounting the capacitor. The MOS capacitor can exhibit excellent high frequency performance. For example, an insertion loss of the MOS capacitor can be greater than about −0.75 dB for frequencies ranging from about 5 GHz to about 40 GHz.

A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.

A capacitor includes: a substrate; a first trench entering the substrate downward from the upper surface of the substrate; a laminated structure provided in the first trench and including m dielectric layers and n conductive layers, the m dielectric layers and the n conductive layers forming a structure that a conductive layer and a dielectric layer are adjacent to each other, each dielectric layer of the m dielectric layers including at least one high-k insulating material with a relative dielectric constant k greater than a first threshold value, and each conductive layer of the n conductive layers including at least one high work function conductive material with a work function greater than a second threshold value, where m and n are positive integers; and a first electrode electrically connected to all odd-numbered conductive layers, and a second electrode electrically connected to all even-numbered conductive layers.

A semiconductor apparatus including a capacitor and a method of manufacturing the same, and an electronic device including the semiconductor apparatus are provided. According to embodiments, the semiconductor apparatus may include: a vertical semiconductor device including an active region extending vertically on a substrate; and a capacitor including a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode sequentially stacked. The first capacitor electrode extends vertically on the substrate and includes a conductive material, and the conductive material includes at least one semiconductor element contained in the active region of the vertical semiconductor device.

Disclosed are devices having a metal-insulator-metal (MIM) capacitor and methods for fabricating the devices. The MIM capacitor includes a plurality of trenches in a Silicon (Si) substrate; a porous Si surface formed in the plurality of trenches, where the porous Si surface has an irregular surface on sidewalls and bottoms of the plurality of trenches; an oxide layer conformally disposed on the porous Si surface; a first plate conformally disposed on the oxide layer; a first dielectric layer conformally disposed on the first plate; and a second plate conformally disposed on the first dielectric, where the first plate, the first dielectric layer, and the second plate, each have an irregular surface that generally conforms to the irregular surface of the porous Si surface.

A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.

A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.

A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die. Including a substrate disposed above the first insulating layer, a second metal interconnect structure disposed above the substrate, a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, and a stacked deep trench capacitor (DTC) structure disposed in the substrate. The DTC structure includes a first plurality of trenches extending from a first side of the substrate and a second plurality of trenches extending from a second side of the substrate.