A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming an opening within the substrate; forming a conductive layer within the opening; and forming a semiconductor layer over the conductive layer.

The passive element includes a semiconductor substrate, a first insulating film, a first metal pad, a first conductor, and a first conductive film. The semiconductor substrate has p-type or n-type conductivity, and has a main surface and a back surface. The first insulating film is provided on a first region in the main surface of the semiconductor substrate. The first metal pad is provided on the first insulating film. The first conductor extends from the first metal pad in the first direction. The first conductive film is provided on a second region adjacent to the first region in a first direction in the main surface of the semiconductor substrate. The first conductive film is in ohmic contact with the main surface of the semiconductor substrate, and has an electrical resistivity lower than an electrical resistivity of the semiconductor substrate.

An integrated circuit device comprising a varactor comprising a first conductive contact; a second conductive contact; and a thin film transistor (TFT) channel material coupled between the first conductive contact and the second conductive contact.