A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures. In the first semiconductor regions, the high-impurity-concentration regions are provided at positions different from positions facing the first electrodes.

A method of manufacturing a semiconductor integrated circuit includes forming a body region having a second conductivity type in an upper portion of a support layer having a first conductivity type and forming a well region having a second conductivity type in an upper portion of the support layer. An output side buried layer is formed inside the body region and a circuit side buried layer is formed inside the well region. A trench is dug to penetrate through the body region and a control electrode structure is buried in the gate trench. First and second terminal regions are formed on the well region and an output terminal region is formed on the body region. An output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.

A module (100) is specified, the module (100) comprising a first module connection (108), a second module connection (109), an energy store (105), a first electrical switch (101) and a second electrical switch (102), wherein a switchable bypass device (1) is arranged between the first module connection (108) and the second module connection (109) and wherein the switchable bypass device (1) is configured to remain in a bidirectional current conducting state in response to a single trigger pulse.

A semiconductor integrated circuit includes: an n.sup.-type support layer; a p-type well region provided in an upper portion of the support layer; a p.sup.+-type circuit side buried layer provided inside the well region; an n.sup.+-type first and second terminal regions provided in an upper portion of the well region and above the circuit side buried layer; a p-type body region provided in an upper portion of the support layer; a control electrode structure provided in a gate trench; a p.sup.+-type output side buried layer provided inside the body region so as to be in contact with the control electrode structure; and an n.sup.+-type output terminal region provided in an upper portion of the body region and above the output side buried layer, wherein an output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.

An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.

A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.

A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.