A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.

A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.

The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, wherein an N-type heavily-doped region 410 and a P-type heavily-doped region 422 which are connected to an anode are provided in the N-Well, and a floating guard ring 416 is further provided in the N-Well between the N-type heavily-doped region 410 and the P-type heavily-doped region 422, the guard ring being spaced from the N-type heavily-doped region 410 by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region 422; and an N-type heavily-doped region 414 and a P-type heavily-doped region 424 which are connected to a cathode are provided in the P-Well.

According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

An electrostatic discharge protection device includes a substrate, first and second emitter regions disposed in the substrate, laterally spaced from one another on a side of the substrate, and having opposite conductivity types, and first and second base regions having opposite conductivity types and in which the first and second emitter regions are disposed in a thyristor arrangement, respectively. The first base region includes a buried doped layer that extends under the second base region. Each of the buried doped layer and the second base region includes a respective non-uniformity in dopant concentration profile. A spacing between the buried doped layer and the second base region at the respective non-uniformities establishes a breakdown trigger voltage for the thyristor arrangement.

The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, wherein an N-type heavily-doped region 410 and a P-type heavily-doped region 422 which are connected to an anode are provided in the N-Well, and a floating guard ring 416 is further provided in the N-Well between the N-type heavily-doped region 410 and the P-type heavily-doped region 422, the guard ring being spaced from the N-type heavily-doped region 410 by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region 422; and an N-type heavily-doped region 414 and a P-type heavily-doped region 424 which are connected to a cathode are provided in the P-Well.

SCRs are a must for ESD protection in low voltagehigh speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

An electrostatic discharge protection device includes a substrate, first and second emitter regions disposed in the substrate, laterally spaced from one another on a side of the substrate, and having opposite conductivity types, and first and second base regions having opposite conductivity types and in which the first and second emitter regions are disposed in a thyristor arrangement, respectively. The first base region includes a buried doped layer that extends under the second base region. Each of the buried doped layer and the second base region includes a respective non-uniformity in dopant concentration profile. A spacing between the buried doped layer and the second base region at the respective non-uniformities establishes a breakdown trigger voltage for the thyristor arrangement.

A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.

A semiconductor device includes a semiconductor body having opposite first and second surfaces, a gate region, and an active region arranged adjacent to the gate region in a horizontal direction. A first emitter, a first base, and a second base are arranged consecutively between the second and first surfaces in a vertical direction. A front-facing emitter is arranged in the active region and extends in the vertical direction from the first surface to the second base. Short-circuit regions extend from the first surface through the front-facing emitter to the second base. The active region has, in the horizontal direction, a first edge region adjacent to the gate region, a failure region adjacent to the first edge region, and a second edge region adjacent to the failure region. An average density of the short-circuit regions in the failure region is lower than in both edge regions.