The present disclosure relates to an electrostatic protection device including an SCR and a manufacturing method thereof. The electrostatic protection device includes a third N+ doped region across an N-type well region and a P-type well region, and a third P+ doped region adjacent to the third N+ doped region. Each of the third N+ doped region and the third P+ doped region has a high doping concentration. In a case that Zener breakdown occurs in a PN junction structure between the third N+ doped region and the third P+ doped region, the SCR is triggered to form a discharge current path. The present disclosure can reduce a trigger voltage of an electrostatic protection device including an SCR, and can provide electrostatic protection devices having different trigger voltages, with high stability and high robustness.

Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P- closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.

An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.

An electrostatic discharge device includes a substrate. A deep doped well of a first conductive type is disposed in the substrate. A drain doped well of the first conductive type is disposed in the substrate above the deep doped well. An inserted doping well of a second conductive type is disposed in the drain doped well, in contact with the deep doped well. A drain region of the first conductive type is in the drain doped well and above the inserted doping well. An inserted drain of the second conductive type is on the inserted doping well and surrounded by the drain region. A source doped well of the second conductive type is disposed in the substrate, abut the drain doped well. A source region is disposed in the source doped well. A gate structure is disposed on the substrate between the drain region and the source region.

A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.

An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the second conductivity is disposed in the first well. The second doping region having the first conductivity is at least partially disposed in the first well and surrounds the first doping region. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The first doping region, the third doping region, the first well and the second well are integrated to form a first parasitic BJT and a second parasitic BJT that have different majority carriers.

A silicon controlled rectifier (SCR) circuit is configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage. The SCR circuit includes a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector. A second bipolar NPN transistor has a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and an emitter electrically connected to the reference voltage. A guard region is configured and arranged to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region.

An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.