Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

During epitaxial growth of an n.sup.-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n.sup.-type lifetime reduced layer is selectively formed in the n.sup.-type drift layer. The n.sup.-type lifetime reduced layer is disposed at a depth that is more than 5 m from a pn junction surface between a p-type anode layer and the n.sup.-type drift layer in a direction toward a cathode side, and the n.sup.-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n.sup.-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is times a thickness of the n.sup.-type drift layer. A vanadium concentration of the n.sup.-type lifetime reduced layer is 1/100 to of a nitrogen concentration of the n.sup.-type lifetime reduced layer.

It is assumed that a defect satisfying relations of Formula 1 and Formula 2 is a first defect, where an off angle is . It is assumed that a defect having an elongated shape when viewed in a direction perpendicular to the second main surface, and satisfying relations of Formula 3 and Formula 4 is a second defect. A value obtained by dividing the number of the second defect by the sum of the number of the first defect and the number of the second defect is greater than 0.5.

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

A method controls an UPS with a system having: first and second terminals, a switch having: first and second switch terminals respectively connected to the first and second terminals; first and second thyristors connected between the first and second switch terminals in anti-parallel; and an inverter connected to the second terminal and the energy store. Switch current and a first potential at the first terminal are detected. In a first fault, where the first potential drops past a first rule and the switch current rises above a second rule: a second potential at the second switch terminal is set using the inverter so the switch current becomes zero. Then the switch current is compared with a second threshold, and if it is exceeded, a first check result is positive, otherwise it's negative. When positive, the second potential is reversed.

A method controls an UPS with a system having: first and second terminals, a switch having: first and second switch terminals respectively connected to the first and second terminals; first and second thyristors connected between the first and second switch terminals in anti-parallel; and an inverter connected to the second terminal and the energy store. Switch current and a first potential at the first terminal are detected. In a first fault, where the first potential drops past a first rule and the switch current rises above a second rule: a second potential at the second switch terminal is set using the inverter so the switch current becomes zero. Then the switch current is compared with a second threshold, and if it is exceeded, a first check result is positive, otherwise it's negative. When positive, the second potential is reversed.

The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

A semiconductor device comprises at least one cell. The structure of each cell comprises: a N-type substrate; at least one first trench unit and at least one second trench unit provided on one side of the N-type substrate; at least one P-type semiconductor region provided on the other side of the N-type substrate, the P-type semiconductor region consisting an anode region; at least one N-type carrier barrier region; and at least one P-type electric field shielding region. The purpose of the present invention is to provide a semiconductor device which has a novel cell structure to provide: a large safe operating area; a short-circuit resistance; elimination of the effect of parasitic thyristors; a low gate-collector charge (Q.sub.GC) to provide a maximum resistance to dv/dt; increase of conductivity modulation at the emitter side to provide a large current density and an extremely low on-voltage drop; a small turn-off loss; and a low process complexity.

A semiconductor device comprises at least one cell. The structure of each cell comprises: a N-type substrate; at least one first trench unit and at least one second trench unit provided on one side of the N-type substrate; at least one P-type semiconductor region provided on the other side of the N-type substrate, the P-type semiconductor region consisting an anode region; at least one N-type carrier barrier region; and at least one P-type electric field shielding region. The purpose of the present invention is to provide a semiconductor device which has a novel cell structure to provide: a large safe operating area; a short-circuit resistance; elimination of the effect of parasitic thyristors; a low gate-collector charge (Q.sub.GC) to provide a maximum resistance to dv/dt; increase of conductivity modulation at the emitter side to provide a large current density and an extremely low on-voltage drop; a small turn-off loss; and a low process complexity.