This electrostatic protection circuit enables a high hold voltage to be set, and acts to accurately prevent breakdown of a protected circuit immediately after power on, and to prevent breakdown or deterioration of a protection device during prolonged normal operation, without connecting a resistance element in parallel to a plurality of circuit blocks connected in series. This electrostatic protection circuit is provided with a plurality of circuit blocks connected in series between a first node and a second node, at least one circuit block out of the plurality of circuit blocks including a thyristor having an anode connected to one end of the at least one circuit block and a cathode connected to the other end of the at least one circuit block. When the potential of the first node is higher than the potential of the second node during normal operation, the voltage between both ends of the other circuit blocks out of the plurality of circuit blocks is smaller than the voltage between the anode and the cathode of the thyristor.

This electrostatic protection circuit enables a high hold voltage to be set, and acts to accurately prevent breakdown of a protected circuit immediately after power on, and to prevent breakdown or deterioration of a protection device during prolonged normal operation, without connecting a resistance element in parallel to a plurality of circuit blocks connected in series. This electrostatic protection circuit is provided with a plurality of circuit blocks connected in series between a first node and a second node, at least one circuit block out of the plurality of circuit blocks including a thyristor having an anode connected to one end of the at least one circuit block and a cathode connected to the other end of the at least one circuit block. When the potential of the first node is higher than the potential of the second node during normal operation, the voltage between both ends of the other circuit blocks out of the plurality of circuit blocks is smaller than the voltage between the anode and the cathode of the thyristor.

A layered structure includes a thyristor and a light-emitting element. The thyristor at least includes four layers. The four layers are an anode layer, a first gate layer, a second gate layer, and a cathode layer arranged in this order. The light-emitting element is disposed such that the light-emitting element and the thyristor are connected in series. The thyristor includes a semiconductor layer having a bandgap energy smaller than bandgap energies of the four layers.

A layered structure includes a thyristor and a light-emitting element. The thyristor at least includes four layers. The four layers are an anode layer, a first gate layer, a second gate layer, and a cathode layer arranged in this order. The light-emitting element is disposed such that the light-emitting element and the thyristor are connected in series. The thyristor includes a semiconductor layer having a bandgap energy smaller than bandgap energies of the four layers.

A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.

A method controls an UPS with a system having: first and second terminals, a switch having: first and second switch terminals respectively connected to the first and second terminals; first and second thyristors connected between the first and second switch terminals in anti-parallel; and an inverter connected to the second terminal and the energy store. Switch current and a first potential at the first terminal are detected. In a first fault, where the first potential drops past a first rule and the switch current rises above a second rule: a second potential at the second switch terminal is set using the inverter so the switch current becomes zero. Then the switch current is compared with a second threshold, and if it is exceeded, a first check result is positive, otherwise it's negative. When positive, the second potential is reversed.

A method controls an UPS with a system having: first and second terminals, a switch having: first and second switch terminals respectively connected to the first and second terminals; first and second thyristors connected between the first and second switch terminals in anti-parallel; and an inverter connected to the second terminal and the energy store. Switch current and a first potential at the first terminal are detected. In a first fault, where the first potential drops past a first rule and the switch current rises above a second rule: a second potential at the second switch terminal is set using the inverter so the switch current becomes zero. Then the switch current is compared with a second threshold, and if it is exceeded, a first check result is positive, otherwise it's negative. When positive, the second potential is reversed.

A silicon controlled rectifier includes a first P region, an N? region, a second P region, and a plurality of N+ regions. The first P region is connected to an anode. The N? region is adjacent the first P region. The second P region is adjacent the N? region such that the N? region is sandwiched between the first P region and the second P region. The plurality of N+ regions are disposed within the second P region. A first N+ region of the plurality of N+ regions is connected to a cathode. A second N+ region of the plurality of N+ regions is connected to a gate.

A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.

A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.