A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Integrated capacitor including a first electrode structure, a second electrode structure, and an interposed dielectric layer structure. The dielectric layer structure includes a layer combination having an SiO.sub.2 layer, an Si.sub.3N.sub.4 layer, and an Si.sub.xN.sub.y layer. The Si.sub.xN.sub.y layer includes a non-stoichiometric silicon nitride material with an increased proportion of silicon.

Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing a bulk substrate with a first doped layer thereon, depositing a first hard mask over the substrate, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a second doped layer over the first doped layer, where the grown second polysilicon material and epitaxially grown second doped layer form a basis for a strap merging the second doped layer and the second polysilicon material.

Various embodiments of the present application are directed towards a trench capacitor with a conductive cap structure. In some embodiments, the trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer overlying the lower capacitor electrode, and an upper capacitor electrode overlying the capacitor dielectric layer. The capacitor dielectric layer and the upper capacitor electrode are depressed into the substrate and define a gap sunken into the substrate. The conductive cap structure overlies and seals the gap on the upper capacitor electrode. In some embodiments, the conductive cap structure comprises a metal layer formed by physical vapor deposition (PVD) and further comprises a metal nitride layer formed overlying the metal layer by chemical vapor deposition (CVD). In other embodiments, the conductive cap structure is or comprises other suitable materials and/or is formed by other deposition processes.

First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Certain aspects of the present disclosure generally relate to a capacitive element. One example capacitive element generally includes a substrate, a plurality of trench capacitors, an electrically conductive via, a first electrically conductive contact, and a second electrically conductive contact. The trench capacitors intersect the substrate. The electrically conductive via intersects the substrate and is disposed adjacent to at least one of the trench capacitors. The first electrically conductive contact is disposed above the substrate, and the second electrically conductive contact is disposed below the substrate and electrically coupled to the plurality of trench capacitors through the electrically conductive via.

A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface that face each other in a thickness direction, the first main surface containing a trench; an insulation layer on a surface of the trench; a first electrode layer on the insulation layer; a first dielectric layer on the first electrode layer; and a second electrode layer on the first dielectric layer, in which a thickness (L.sub.1) of the insulation layer, a thickness (L.sub.2) of the first electrode layer, and a thickness (L.sub.4) of the second electrode layer satisfy L.sub.1>L.sub.2>L.sub.4.

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

A semiconductor device has: a semiconductor substrate; a trench that extends from a first surface of the semiconductor substrate towards an interior of the semiconductor substrate, and that has a recess/protrusion structure on a side wall surface thereof; a semiconductor film that is formed so as to cover the side wall surface of the trench, be continuous with the side wall surface, and extend onto the first surface of the semiconductor substrate; an opposite electrode having a first portion that is provided at a position opposing the semiconductor substrate while sandwiching the semiconductor film therebetween, and that extends on the first surface of the semiconductor substrate, and a second portion that is continuous with the first portion and extends so as to fill the trench; and an insulating film that insulates the semiconductor film from the opposite electrode.