METHOD FOR CONNECTING COMPONENTS DURING PRODUCTION OF POWER ELECTRONIC MODULES OR ASSEMBLIES

Abstract

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

Claims

1. Method for connecting components during production of power electronics modules or assemblies which in particular include one or more semiconductor elements (4) on a substrate (3) or on each other, in which surfaces of the components that are to be connected are supplied with an existing metallic surface layer (1) or furnished therewith, which layer has a surface that is sufficiently smooth to allow direct bonding or that is polished to obtain a surface that is sufficiently smooth to allow direct bonding, and the surface layers (1) of the surfaces to be connected are pressed against each other with a pressure of at least 5 MPa at elevated temperature so that they are connected to each other, forming a single layer (2).

2. Method according to claim 1, characterized in that the surface layers (1) of the surfaces to be connected are pressed against each other with a pressure of >10 MPa.

3. Method according to claim 1, characterized in that the surfaces of the components that are to be connected are provided with an existing surface layer (1) of Ag or a metallic material containing Ag as its major constituent, or are coated with such a layer as said metallic surface layer (1).

4. Method according to claim 1, characterized in that one or more of the semiconductor elements (4) as components are connected to the substrate (3).

5. Method according to claim 1, characterized in that several of the semiconductor elements (4) as components are connected to each other, forming a component stack.

6. Method according to claim 1, characterized in that one or more of the semiconductor elements (4) as components are connected with one or more electrical connecting elements (5) in the form of strips.

7. Method according to claim 1, characterized in that the surface layers (1) are structured before the connection, or are already structured when supplied such that individual layer regions of the layer (2) formed are electrically insulated from each other by gaps (7) after the connection.

8. Method according to claim 1, characterized in that the surface layers (1) are structured before the connection, or are already structured when supplied such that recesses are formed, wherein an insulating material (6) is introduced into one or more of the recesses in the surface layers (1) before the connection.

9. Method according to claim 8, characterized in that the insulating material (6) and the elevated temperature are selected such that the insulating material (6) melts during the connection of the surface layers (1) due to the elevated temperature.

10. Method according to claim 8, characterized in that a glass material is used as the insulating material (6).

11. Power electronics module including one or more semiconductor elements (4) on a substrate (3), wherein one or more components of the power electronics module is/are connected to each other by the method according to claim 1.

12. Power electronics module according to claim 11, characterized in that one or more of the semiconductor elements (4) as components are connected to the substrate (3) by the method.

13. Power electronics assembly including one or more semiconductor elements (4), wherein one or more components of the power electronics assembly are connected to each other by the method according to claim 1.

14. Power electronics module or power electronics assembly according to claim 11, characterized in that several of the semiconductor elements (4) as components are connected to each other by the method, forming a component stack.

15. Power electronics module or power electronic assembly according to claim 11, characterized in that one or more of the semiconductor elements (4) as components are connected to one or more electrical connecting elements (5) designed in the form of strips by the method.

16. Power electronics assembly according to claim 13, characterized in that several of the semiconductor elements (4) as components are connected to each other by the method, forming a component stack.

17. Power electronics assembly according to claim 13, characterized in that one or more of the semiconductor elements (4) as components are connected to one or more electrical connecting elements (5) designed in the form of strips by the method.

Description

BRIEF DESCRIPTION OF THE DRAWING

[0017] In the following text, the suggested method will be explained again in greater detail with reference to exemplary embodiments and in conjunction with the drawing. In the drawing:

[0018] FIG. 1 shows an example of the connection of two ultrathin semiconductor elements to a substrate according to the suggested method;

[0019] FIG. 2 shows an example of stacking of two semiconductor diodes according to the suggested method;

[0020] FIG. 3 shows an example of the connection of a semiconductor element to a substrate using additional insulating material according to the suggested method;

[0021] FIG. 4 shows an example of the electrical connection of a semiconductor element to a contact pad on the substrate via an electrical connecting element according to the suggested method;

[0022] FIG. 5 shows examples of stacking MOSFETs on each other (sub-image A) and connection of MOSFETs to a substrate (sub-image B) according to the suggested method;

[0023] FIG. 6 shows an example of the connection of MOSFETs to two substrates according to the suggested method;

[0024] FIG. 7 shows examples of stacking MOSFETs on and beside a vertical Si-capacitor, and the connection with a substrate according to the suggested method;

[0025] FIG. 8 shows an example of an alternative arrangement to the arrangement of FIG. 7;

[0026] FIG. 9 shows an example of stacking MOSFETs on a lateral Si-capacitor according to the suggested method; and

[0027] FIG. 10 shows an example of an alternative arrangement to the arrangement of FIG. 9.

WAYS TO IMPLEMENT THE INVENTION

[0028] In the suggested method, surfaces of the components of a power electronics module or a power electronics assembly to be connected are joined using the technique of direct metal diffusion bonding. This not only enables semiconductor elements of the power electronics module to be connected to the substrate, but also 3D stacking of the semiconductor elements or element chips on the substrate. This in turn enables innovative circuitry concepts to be created by 3D power integration, which combine excellent high frequency properties with a mechanically rugged, low-loss substrate.

[0029] The suggested method also enables the connection of ultrafine wide bandgap elements having a thickness of <20 μm to the substrate, or also to each other or to other semiconductor elements. This is represented schematically in FIG. 1, in which two such ultrathin semiconductor elements 4, in the present case made from GaN and SiC, are connected to the substrate 3 of the power electronics module, made for example from Si, SiC, Cu or another suitable material. For this purpose, a metallic surface layer, in this and the following examples a layer of crystalline Ag 1, is applied to the surface of the substrates 3 and structured for the subsequent function of an electrical circuit or electrical connections. Similarly, an Ag layer 1 is also applied to the underside of the semiconductor element 4. These surface layers are brought into contact with each other, and the respective components 4 are pressed against each the substrate 3 with correspondingly high pressure, in the present examples in a range from >10 to 35 MPa, and at elevated temperature, in the case of Ag layers preferably in the range between 240° C. and 280° C., for about 1 to 15 minutes. In this way, the Ag layers 1 arranged next to each other are joined to form a single connecting layer (not discernible in FIG. 1). In this case, the structuring of the Ag layers 1 formed an insulating gap 7 during the connection, which insulates the individual regions of the connecting layer formed from each other. In the example of FIG. 1, a corresponding Ag layer 1 is also applied to the upper side of the elements 4, which enables either a contacting between these elements during subsequent processing or also a stacking of additional semiconductor elements.

[0030] FIG. 2 shows an example of stacking two diodes as semiconductor elements 4 to accomplish a serial connection o of the diodes as represented in the bottom part of the figure. In this example, both sides of the two diodes again have an Ag layer 1 as the metallic surface layer, they are the placed one on top the other and connected to each other by direct bonding through the application of pressure at elevated temperature. In this connection, the two Ag layers 1 lying one on top of the other form a single Ag layer as connecting layer 2, as is suggested in the portion of the figure on the right. Of course, such a stack of two semiconductor elements 4 in power electronic modules can also be made with other semiconductor elements such as transistors or capacitors and also with more than two semiconductor elements 4. The contact surfaces of such semiconductor elements in power electronics modules typically have a surface area of at least 2×2 mm.sup.2.

[0031] In order to insulate individual layer regions of the connecting layer 2 which is created by the connection from each other, additional insulators besides a pure structuring such as in FIG. 1 may also be used, as is represented by way of example in conjunction with FIG. 3. In this example, again the Ag layers 1 are first structured. Then, an insulating material 6 is introduced into corresponding recesses or also locally onto the surface of said layers 1, as is indicated schematically in the left portion of FIG. 3. In this example, a glass material is used as insulating material 6. Then while the two Ag layers 1 are connected to each other by the application of pressure at elevated temperature, the electrically insulating connection points are also bonded with each other materially, thereby forming corresponding insulation in the joint thus created, as may be seen in the portion on the right of FIG. 3. In this context, the material connection is made as a result of the elevated temperature, for example by sintering, by chemical reaction, or in particular—as in this example—by fusing. When a glass material is used as the insulating material 6, the glass material and the temperatures used when making the connection are tuned to each other in such manner that the glass material melts and correspondingly joins with itself in a material bond.

[0032] The suggested method also enables the electrical connection of individual regions of the power electronics module via corresponding electrical connecting elements 5, which in this case have the form of strips. In this case too, an Ag layer 1 is applied to the respective contact surfaces as is shown in the left portion of FIG. 4. The corresponding contact surfaces are then joined by the application of pressure at elevated temperature, and form a single, cohesive Ag and connecting layer 2 (compare with the portion of FIG. 4 on the right.

[0033] FIGS. 5 and 6 show examples of different ways to create a circuit represented in the top part of FIG. 5A. Accordingly, in the example of FIG. 5A the two MOSFETs as semiconductor elements 4 are stacked one above the other in such a way as to create the circuitry of these transistors as represented in the top part of the figure. In this case, the connection is again made by direct bonding with suitable metallic surface layers, in this example Ag layers 1, which are structured suitably in advance.

[0034] FIG. 5B shows an alternative option, in which the two MOSFETs are arranged side by side on the substrate 3 and connected to the substrate 3. FIG. 6 in turn shows an example of a connection in which a further substrate 3 is placed over the two MOSFETs which are arranged side by side on the substrate 3 in order to create the corresponding connection via the Ag layers 1 required for the connection and an additional electrical connecting element 8. In this case, the individual components are again connected by direct meal bonding according to the suggested method.

[0035] Finally, FIGS. 7 to 10 show a further example in which a circuit with an additional capacitor as illustrated in the top part of FIG. 7 is accomplished. In the example of FIG. 7, the vertical capacitor 9 and the two MOSFETs are stacked one on top of the other on the substrate. The electrical connection of the top MOSFET with the metallisation on the substrate 3 may be realised either via a bonding wire 10 also in similar manner to that shown in FIG. 4. The same applies for the second alternative shown in FIG. 7, in which the vertical capacitor 9 is arranged beside the stack of two MOSFETs on the substrate 3. FIG. 8 shows a further alternative, in which the two MOSFETs are arranged side by side on the substrate 3 and the vertical capacitor 9 is stacked on top of one of the two MOSFETs.

[0036] Whereas in FIGS. 7 and 8 a vertical Si capacitor was used, FIGS. 9 and 10 illustrate a variant with a lateral Si capacitor 9, on which the two MOSFETs in FIG. 9 are stacked. In contrast, FIG. 10 shows an arrangement of the two MOSFETs side by side on the capacitor.

LIST OF REFERENCE NUMERALS

[0037] 1 Ag layer [0038] 2 Connecting layer [0039] 3 Substrate [0040] 4 Semiconductor element [0041] 5 Electrical connecting element [0042] 6 Insulating material [0043] 7 Insulating gap [0044] 8 Electrical connecting element [0045] 9 Capacitor [0046] 10 Bonding wire