A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second through via, a molding material, a second semiconductor die, and a second redistribution layer. The first semiconductor die is disposed over the first redistribution layer and includes a first through via having a first width. The second through via is adjacent to the first semiconductor die and has a second width. The second width is greater than the first width. The molding material surrounds the first semiconductor die and the second through via. The second semiconductor die is disposed over the molding material and is electrically coupled to the first through via and the second through via. The second redistribution layer is disposed over the second semiconductor die.

A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.

A semiconductor structure includes a substrate, comprising a first doped region; a first dielectric layer, located on the substrate; multiple deep trench capacitors, extending from the first dielectric layer to an inside of the substrate, in which each of the deep trench capacitors penetrates through the first doped region and comprises a serrated inner wall; multiple second doped regions, located in the substrate, in which each of the second doped regions surrounds a bottom of each deep trench capacitor and extends into the first doped region along an outer wall of the deep trench capacitor; and a first metal layer, located on the first dielectric layer and connected with the multiple deep trench capacitors.

A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

A semiconductor device includes: a semiconductor substrate; a first semiconductor layer; a first conductor; a first power supply line; a second power supply line; and a circuit. The semiconductor substrate has a first surface, a second surface facing the first surface, and a third surface disposed between the first surface and the second surface. The first semiconductor layer is disposed along the first surface from the third surface. The first conductor is disposed on the first semiconductor layer. The first power supply line is electrically connected to the first conductor. The second power supply line is electrically connected to the semiconductor substrate. The circuit is disposed on the semiconductor substrate and connected to the first power supply line and the second power supply line.

Capacitor comprising: a first porous semiconductor having an average pore size of between 20 nm and 200 nm and preferably between 40 nm and 100 nm, at least one second electric conductor, wherein the second electric conductor infiltrates the porous structure, and the materials involved are selected such that a potential barrier is formed between the first porous semiconductor and the second conductor, without applying an external voltage, as a result of the diffusion of charge carriers, which is preferably more than 0.5 V, more preferably more than 0.7 V, more preferably more than 1 V, and more preferably still more than 1.4 V, wherein a dielectric layer having a thickness of 1 nm to 10 nm is preferably arranged between the first porous semiconductor and the second electric conductor.

Disclosed are semiconductor packages and semiconductor devices. In one embodiment, a semiconductor package includes a package, a first integrated passive device, and a second integrated passive device. The first integrated passive device is disposed below the package. The second integrated passive device is disposed between the package and the first integrated passive device. The first integrated passive device is electrically connected to the package through the second integrated passive device.

In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die. Including a substrate disposed above the first insulating layer, a second metal interconnect structure disposed above the substrate, a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, and a stacked deep trench capacitor (DTC) structure disposed in the substrate. The DTC structure includes a first plurality of trenches extending from a first side of the substrate and a second plurality of trenches extending from a second side of the substrate.

A semiconductor package includes an integrated circuit (IC) structure, an insulating encapsulation laterally covering the IC structure, and a redistribution structure disposed on the insulating encapsulation and the IC structure. The redistribution structure is electrically connected to the IC structure. The IC structure includes a first die, a capacitor structure, a dielectric layer laterally covering the first die and the capacitor structure, and a second die disposed on the dielectric layer, the first die, and the capacitor structure. The second die interacts with the capacitor structure, where a bonding interface between the second die and the first die is substantially coplanar with a bonding interface between the second die and the dielectric layer. A manufacturing method of a semiconductor package is also provided.