The stack capacitor structure includes a substrate, first, second, third, and fourth support layers, first, second, and third insulating layers, first, second, and third holes, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from the second support layer to the first support layer. The second and third holes penetrate through from the fourth support layer to the third support layer. The capacitor is disposed in the first, second, and third holes.

A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

Provided is a semiconductor storage device and an electronic apparatus having a structure that is more suitable for miniaturization and high integration of memory cells. A semiconductor storage device includes: a recessed portion provided in a semiconductor substrate; a ferroelectric film provided along an inner side of the recessed portion; an electrode provided on the ferroelectric film so as to be embedded in the recessed portion; a first conductivity-type separation region provided in the semiconductor substrate under the recessed portion; and a second conductivity-type electrode region provided in the semiconductor substrate on at least one side of the recessed portion.

An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

A capacitor includes: a semiconductor substrate including at least one substrate trench group; at least one laminated structure, each laminated structure includes n conductive layers and m dielectric layers, the first conductive layer in the n conductive layers is disposed above the semiconductor substrate and in the substrate trench group, the i-th conductive layer in the n conductive layers is provided with the i-th conductive layer trench group, and the (i+1)th conductive layer in the n conductive layers is disposed above the i-th conductive layer and in the i-th conductive layer trench group, where m, n, and i are positive integers, and n≥2, 1≤i≤n−1; a first external electrode connected to some conductive layers; and a second external electrode connected to other conductive layers.

A semiconductor device is provided that includes a semiconductor substrate having a first main surface and a second main surface facing each other; a dielectric layer laminated on the first main surface of the semiconductor substrate; a first electrode layer laminated on the dielectric layer; and a protective layer covering at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer. Moreover, the protective layer is provided to expose an outer peripheral end on the first main surface of the semiconductor substrate. The semiconductor substrate includes a high-resistance region positioned at least directly under an outer peripheral end of the protective layer.

An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

Present disclosure provide a capacitor includes: a semiconductor substrate; a laminated structure including n conductive layers and m dielectric layer(s), the i-th conductive layer being provided with at least one i-th isolation trench, the (i+1)-th conductive layer being provided above the i-th conductive layer and in the i-th isolation trench, isolation trenches in odd-numbered and even-numbered conductive layers having a first and a second overlap region in a vertical direction respectively, and the first overlap region not overlapping the second overlap region, where m, n, and i are positive integers, n≥2, and 1≤i≤n−1; at least one first external electrode electrically connected to all odd-numbered conductive layer(s) through a first conductive via structure in the second overlap region; and at least one second external electrode electrically connected to all even-numbered conductive layer(s) through a second conductive via structure in the first overlap region.

There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor:

wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric;
the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and
the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.