According to the embodiments provided herein, a method for doping an absorber layer can include contacting the absorber layer with an annealing compound. The annealing compound can include cadmium chloride and a group V salt comprising an anion and a cation. The anion, the cation, or both can include a group V element. The method can include annealing the absorber layer, whereby the absorber layer is doped with at least a portion of the group V element of the annealing compound.

Provided is a stable CdZnTe monocrystalline substrate having a small leakage current even when a high voltage is applied and having a lower variation in resistivity with respect to variations in applied voltage values. A semiconductor wafer comprising a cadmium zinc telluride monocrystal having a zinc concentration of 4.0 at % or more and 6.5 at % or less and a chlorine concentration of 0.1 ppm by mass or more and 5.0 ppm by mass or less, wherein the semiconductor wafer has a resistivity of 1.0×10.sup.7 Ωcm or more and 1.0×10.sup.8 Ωcm or less when a voltage of 900 V is applied, and wherein a ratio (variation ratio) of the resistivity at application of 0 V to the resistivity at application of a voltage of 900 V is 20% or less.

Solar cells, absorber structures, back contact structures, and methods of making the same are described. The solar cells and absorber structures include a pseudomorphically strained electron reflector layer.

Monolithic pixel detectors, systems and methods for the detection and imaging of electromagnetic radiation with high spectral and spatial resolution comprise a Si wafer with a CMOS processed pixel readout bonded to an absorber wafer in wafer bonds comprising conducting bonds between doped, highly conducting charge collectors in the readout and highly conducting regions in the absorber wafer and poorly conducting bonds between regions of high resistivity.

Disclosed herein are CdSeTe photovoltaic devices having interdigitated back contact architecture for use in polycrystalline thin films in photovoltaic devices.

According to the embodiments provided herein, a method for forming a photovoltaic device can include depositing a plurality of semiconductor layers. The plurality of semiconductor layers can include a doped layer that is doped with a group V dopant. The doped layer can include cadmium selenide or cadmium telluride. The method can include annealing the plurality of semiconductor layers to form an absorber layer.

According to an aspect, there is provided a structure comprising an absorbing layer for absorbing incident infrared radiation received via a receiving surface of the absorbing layer and a plurality of mushroom-shaped plasmonic elements for enhancing absorption of the incident infrared radiation into the absorbing layer. Said plurality of mushroom-shaped plasmonic elements have sub-wavelength dimensions and sub-wavelength spacings and are arranged along the receiving surface. Each of said plurality of mushroom-shaped plasmonic elements project out relative to the receiving surface.

Provided is a CdZnTe monocrystalline substrate which has a small leakage current even when a voltage is applied from a low voltage to a high voltage, and which has a lower variation in resistivity with respect to applied voltage changes from 0 to 900 V, and which can maintain a stable resistivity. A semiconductor wafer comprising a cadmium zinc telluride monocrystal having a zinc concentration of 4.0 at % or more and 6.5 at % or less and a chlorine concentration of 0.1 ppm by weight or more and 5.0 ppm by weight or less, wherein when a voltage is applied in a range of from 0 to 900 V, the semiconductor wafer has a resistivity for each applied voltage value of 1.0×10.sup.7 Ωcm or more and 7.0×10.sup.8 Ωcm or less, and wherein a relative variation coefficient of each resistivity to the applied voltages in a range of from 0 to 900 V is 100% or less.

Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.

Disclosed herein are a radiation detector and a method of making it. The radiation detector is configured to absorb radiation particles incident on a semiconductor single crystal of the radiation detector and to generate charge carriers. The semiconductor single crystal may be a CdZnTe single crystal or a CdTe single crystal. The method may comprise forming a recess into a substrate of semiconductor; forming a semiconductor single crystal in the recess; and forming a heavily doped semiconductor region in the substrate. The semiconductor single crystal has a different composition from the substrate. The heavily doped region is in electrical contact with the semiconductor single crystal and embedded in a portion of intrinsic semiconductor of the substrate.