One embodiment provides a semiconductor device comprising: a substrate; a first semiconductor layer disposed on the substrate; a second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer disposed on the second semiconductor layer; and a reflective layer disposed on the third semiconductor layer, wherein the part between the first and second semiconductor layers, the part between the third and second semiconductor layers, and the second semiconductor layer comprise a depletion region, and the conductivity of the first semiconductor layer and the conductivity of the third semiconductor layer are different from each other, and the second semiconductor layer comprises an intrinsic semiconductor layer.

Method for producing a photoemitting or photoreceiving diode, including: producing, on a first substrate, first and second semiconductor layers with opposite dopings, and a third intrinsic semiconductor layer; etching trenches surrounding remaining portions of the second and third layers and of a first part of the first layer; producing, in the trenches, a dielectric spacer covering side walls of said remaining portions; etching extending the trenches as far as the first substrate; laterally etching a part of the dielectric spacer, exposing contact surfaces of the second part of the first layer; producing, in the trenches, a first electrode in contact with the contact surfaces of the second part of the first layer and with lateral flanks of the second part of the first layer.

A physical vapor deposition (e.g., sputter deposition) method for III-nitride tunnel junction devices uses metal-organic chemical vapor deposition (MOCVD) to grow one or more light-emitting or light-absorbing structures and electron cyclotron resonance (ECR) sputtering to grow one or more tunnel junctions. In another method, the surface of the p-type layer is treated before deposition of the tunnel junction on the p-type layer. In yet another method, the whole device (including tunnel junction) is grown using MOCVD and the p-type layers of the III-nitride material are reactivated by lateral diffusion of hydrogen through mesa sidewalls in the III-nitride material, with one or more lateral dimensions of the mesa that are less than or equal to about 200 μm. A flip chip display device is also disclosed.

A method for fabricating a neutron detector includes providing an epilayer wafer of Boron-10 enriched hexagonal boron nitride (h-.sup.10BN or h-BN or .sup.10BN or BN) having a thickness (t), dicing or cutting the epilayer wafer into one or more BN strips having a width (W) and a length (L), and depositing a first metal contact on a first surface of at least one of the BN strip and a second metal contact on a second surface of the at least one BN strip. The neutron detector includes an electrically insulating submount, a BN epilayer of Boron-10 enriched hexagonal boron nitride (h-.sup.10BN or h-BN or .sup.10BN or BN) placed on the insulating submount, a first metal contact deposited on a first surface of the BN epilayer, and a second metal contact deposited on a second surface of the BN epilayer.

An optoelectronic semiconductor structure includes a first n-type semiconductor layer, a first quantum well layer, a first p-type semiconductor layer, and a second n-type semiconductor layer. The first quantum well layer is disposed on the first n-type semiconductor layer. The first p-type semiconductor layer is disposed on the first quantum well layer. The second n-type semiconductor layer is disposed on the first p-type semiconductor layer. The second n-type semiconductor layer includes both an n-type dopant and a p-type dopant. The concentration of the n-type dopant in the second n-type semiconductor layer is greater than the concentration of the p-type dopant in the second n-type semiconductor layer. The first n-type semiconductor layer, the first quantum well layer, the first p-type semiconductor layer, and the second n-type semiconductor layer form a bipolar phototransistor structure. A manufacturing method of the optoelectronic semiconductor structure is also provided.

An InGaN-based resonant cavity enhanced detector chip based on porous DBR, including: a substrate (10); a buffer layer (11) formed on the substrate (10); a bottom porous DBR layer (12) formed on the buffer layer (11); an n-type GaN layer (13) formed on the bottom porous DBR layer (12), wherein one side of the n-type GaN layer (13) is recessed downward to form a mesa (13), and the other side of the n-type GaN layer (13) is protruded; an active region (14) formed on the n-type GaN layer (13); a p-type GaN layer (15) formed on the active region (14); a sidewall passivation layer (20) formed on an upper surface of the p-type GaN layer (15) and sidewalls of the protruded n-type GaN layer (13), the active region (14), and the p-type GaN layer (15), wherein the sidewall passivation layer (20) on the upper surface of the p-type GaN layer (15) has a window in a middle; a transparent conductive layer (16) formed on the sidewall passivation layer (20) and the p-type GaN layer (15) at the window; an n-type electrode (18) formed on the mesa of the n-type GaN layer (13); a p-type electrode (19) formed on a periphery of an upper surface of the sidewall passivation layer (20); a top dielectric DBR layer (17) formed on the transparent conductive layer (16) and the p-type electrode (19).

A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands.

Semiconductor devices and methods of fabricating semiconductor devices having a dilute nitride layer and at least one semiconductor material overlying the dilute nitride layer are disclosed. Hybrid epitaxial growth and the use of aluminum barrier layers to minimize hydrogen diffusion into the dilute nitride layer are used to fabricate high-efficiency multijunction solar cells.

Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.

An opto-electronic High Electron Mobility Transistor (HEMT) may include a current channel including a two-dimensional electron gas (2DEG). The opto-electronic HEMT may further include a photoelectric bipolar transistor embedded within at least one of a source and a drain of the HEMT, the photoelectric bipolar transistor being in series with the current channel of the HEMT.