A solar cell of an embodiment includes a p-electrode, a p-type light-absorbing layer directly in contact with the p-electrode, an n-type layer, and an n-electrode. The n-type layer is disposed between the p-type light-absorbing layer and the n-electrode. A region from an interface between the p-type light-absorbing layer and the p-electrode to 10 nm to 100 nm from the interface in a direction of the n-type layer is a p+ type region including a p-type dopant.

A method for manufacturing a stacked thin film, includes forming a photoelectric conversion layer on a first transparent electrode by sputtering using a target mainly composed of copper in an oxygen containing atmosphere. An oxygen partial pressure of the sputtering is in a range of 0.01 [Pa] or more and 4.8 [Pa] or less, and 0.24×d [Pa] or more and 2.4×d [Pa] or less when a deposition rate is d [μm/min], in formation of the photoelectric conversion layer. A sputtering temperature is 300° C. or more and 600° C. or less, in formation of the photoelectric conversion layer.

Provided is a method of manufacturing a synaptic device. The method includes forming a first electrode, forming a synaptic mimic layer including a hole transport layer and an electron transport layer on the first electrode, and forming a second electrode on the synaptic mimic layer, wherein the forming of the synaptic mimic layer includes forming the electron transport layer on the hole transport layer through a solution process.

Provided is a method of manufacturing a synaptic device. The method includes forming a first electrode, forming a synaptic mimic layer including a hole transport layer and an electron transport layer on the first electrode, and forming a second electrode on the synaptic mimic layer, wherein the forming of the synaptic mimic layer includes forming the electron transport layer on the hole transport layer through a solution process.

A photovoltaic (PV) device having a quantum dot sensitized interface includes a first conductor layer and a second conductor layer. At least one of the conductor layers is transparent to solar radiation. A quantum dot (nanoparticle) sensitized photo-harvesting interface comprises a photo-absorber layer, a quantum dot layer and a buffer layer, placed between the two conductors. The absorber layer is a p-type material and the buffer layer is an n-type material. The quantum dot layer has a tunable bandgap to cover infrared (IR), visible light and ultraviolet (UV) bands of solar spectrum.

A photovoltaic (PV) device having a quantum dot sensitized interface includes a first conductor layer and a second conductor layer. At least one of the conductor layers is transparent to solar radiation. A quantum dot (nanoparticle) sensitized photo-harvesting interface comprises a photo-absorber layer, a quantum dot layer and a buffer layer, placed between the two conductors. The absorber layer is a p-type material and the buffer layer is an n-type material. The quantum dot layer has a tunable bandgap to cover infrared (IR), visible light and ultraviolet (UV) bands of solar spectrum.

A positive-intrinsic-negative (PIN) photosensitive device is provided. A p-type semiconductor layer composed of molybdenum oxide and having valence band energy between valence band energy of an intrinsic semiconductor layer and an upper electrode is used to replace a p-type semiconductor layer used in a conventional PIN photodiode, so that the PIN photodiode may be prepared without using borane gas. More, a difference between valence band energy of the p-type semiconductor layer and the intrinsic semiconductor layer is used to transport holes located in a valence band, so that it is unnecessary to use an active layer of a thin film transistor, so that the PIN photosensitive device may be stacked on the thin film transistor to reduce aperture ratio loss of a display panel.

A positive-intrinsic-negative (PIN) photosensitive device is provided. A p-type semiconductor layer composed of molybdenum oxide and having valence band energy between valence band energy of an intrinsic semiconductor layer and an upper electrode is used to replace a p-type semiconductor layer used in a conventional PIN photodiode, so that the PIN photodiode may be prepared without using borane gas. More, a difference between valence band energy of the p-type semiconductor layer and the intrinsic semiconductor layer is used to transport holes located in a valence band, so that it is unnecessary to use an active layer of a thin film transistor, so that the PIN photosensitive device may be stacked on the thin film transistor to reduce aperture ratio loss of a display panel.

A radiation sensor includes a radiation-sensitive semiconductor layer, a cathode electrode disposed over a front side of the radiation-sensitive semiconductor layer that is configured to be exposed to radiation, at least one anode electrode disposed over a backside of the radiation-sensitive semiconductor layer, and a potential barrier layer located between the cathode electrode and the front side of the radiation-sensitive semiconductor layer.

Examples described herein relate to an avalanche photodiode (APD) and an optical receiver including the APD. The APD may include a substrate and a photon absorption region disposed on the substrate. The substrate may include a charge carrier acceleration region under the photon absorption region; a charge region adjacent to the charge carrier acceleration region; and a charge carrier multiplication region adjacent to the charge region. The charge carrier acceleration region, the charge region, and the charge carrier multiplication region are laterally formed in the substrate. When a biasing voltage is applied to the optoelectronic device, photon-generated free charge carriers may be generated in the photon absorption region and are diffused into the charge carrier acceleration region. The charge carrier acceleration region is configured to accelerate the photon-generated free charge carriers prior to the photon-generated free charge carriers entering into the charge region and undergoing impact ionization in the charge carrier multiplication region.