Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a solar cell can include a substrate having a light-receiving surface and a back surface. A first doped region of a first conductivity type, wherein the first doped region is disposed in a first portion of the back surface. A first thin dielectric layer disposed over the back surface of the substrate, where a portion of the first thin dielectric layer is disposed over the first doped region of the first conductivity type. A first semiconductor layer disposed over the first thin dielectric layer. A second doped region of a second conductivity type in the first semiconductor layer, where the second doped region is disposed over a second portion of the back surface. A first conductive contact disposed over the first doped region and a second conductive contact disposed over the second doped region.

A solar cell and a photovoltaic module including the same are provided. The solar cell includes a substrate having a first surface and a second surface opposite to each other; a first passivation stack disposed on the first surface and including a first oxygen-rich dielectric layer, a first silicon-rich dielectric layer, a second oxygen-rich dielectric layer, and a second silicon-rich dielectric layer that are sequentially disposed in a direction away from the first surface, wherein an atomic fraction of oxygen in the first oxygen-rich dielectric layer is less than an atomic fraction of oxygen in the second oxygen-rich dielectric layer; a tunneling oxide layer disposed on the second surface; a doped conductive layer disposed on a surface of the tunneling oxide layer; and a second passivation layer disposed on a surface of the doped conductive layer.

The present disclosure provides a method for rapidly treating a heterojunction solar cell fabricated using a crystalline silicon wafer doped exclusively with n-type dopants to improve surface passivation and carrier transport properties using the following steps: providing a heterojunction solar cell; the solar cell having an n-type silicon substrate exclusively doped with n-type dopants with a concentration higher than 1×10.sup.14 cm.sup.−3 and a plurality of metallic contacts; illuminating a surface portion of the solar cell for a period of less than 5 minutes and at a temperature between 200° C. and 300° C. with light having an intensity of at least 2 kW/m.sup.2 and a wavelength such that the light is absorbed by the surface portion and generates electron-hole pairs in the solar cell. The step of illuminating a surface portion of the solar cell is such that less than 0.5 kWh/m.sup.2 of energy is transferred to the surface portion and a temperature of the surface portion increases at a rate of at least 10° C./s for a period of time during illumination.

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Photovoltaic devices with very high breakdown voltages are described herein. Typical commercial silicon photovoltaic devices have breakdown voltages below 50-100 volts (V). Even though such devices have bypass diodes to prevent photovoltaic cells from going into breakdown, the bypass diodes have high failure rates, leading to unreliable devices. A high-efficiency silicon photovoltaic cell is provided with very high breakdown voltages. By combining a device architecture with very low surface recombination and silicon wafers with high bulk resistivity (above 10 ohms centimeter (Ω-cm)), embodiments described herein achieve breakdown voltages close to 1000 V. These photovoltaic cells with high breakdown voltages improve the reliability of photovoltaic devices, while reducing their design complexity and cost.

A photovoltaic device including: a first amorphous semiconductor layer (3) and a second amorphous semiconductor layer (4) both on a back face of a semiconductor substrate (1); electrodes (5, 6); and a wiring board (8). The electrodes (5, 6) are disposed on the first amorphous semiconductor layer (3) and the second amorphous semiconductor layer (4) respectively. The wiring board (8) has wires (82) connected to the electrodes (5) by a conductive adhesive layer (7). The wiring board (8) has wires (83) connected to the electrodes (5) by the conductive adhesive layer (7). The electrodes (5) include conductive layers (51, 52). The electrodes (6) include conductive layers (61, 62). The conductive layers (51, 61) are composed primarily of silver. The conductive layers (52, 62) cover the conductive layers (51, 52) respectively. Each conductive layer (52, 62) is composed of a metal more likely to be oxidized than silver.

A photovoltaic device including: a first amorphous semiconductor layer (3) and a second amorphous semiconductor layer (4) both on a back face of a semiconductor substrate (1); electrodes (5, 6); and a wiring board (8). The electrodes (5, 6) are disposed on the first amorphous semiconductor layer (3) and the second amorphous semiconductor layer (4) respectively. The wiring board (8) has wires (82) connected to the electrodes (5) by a conductive adhesive layer (7). The wiring board (8) has wires (83) connected to the electrodes (5) by the conductive adhesive layer (7). The electrodes (5) include conductive layers (51, 52). The electrodes (6) include conductive layers (61, 62). The conductive layers (51, 61) are composed primarily of silver. The conductive layers (52, 62) cover the conductive layers (51, 52) respectively. Each conductive layer (52, 62) is composed of a metal more likely to be oxidized than silver.

Discussed is a solar cell including a semiconductor substrate, a conductive region disposed in the semiconductor substrate or over the semiconductor substrate, and an electrode electrically connected to the conductive region. The electrode includes a first electrode part and a second electrode part disposed over the first electrode part. The second electrode part includes a particle connection layer formed by connecting a plurality of particles including a first metal and a cover layer including a second metal different from the first metal and covering at least the outside surface of the particle connection layer.

A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.