A high efficiency configuration for a solar cell module comprises solar cells conductively bonded to each other in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency.

Provided are a solar cell, a method for manufacturing a solar cell and a photovoltaic module. The solar cell includes a semiconductor substrate including a surface having a first texture structure and a first passivation layer located on the first texture structure of the semiconductor substrate. The first texture structure includes a pyramid-shaped microstructure, a length of a bevel edge of the pyramid-shaped microstructure is C μm, and 0.4≤C≤1.9. A non-uniformity of the first passivation layer is N≤4%, and N=(D.sub.max−D.sub.min)/D.sub.max. D.sub.max is a maximum thickness of the first passivation layer on the pyramid-shaped microstructure, and D.sub.min is a minimum thickness of the first passivation layer on the pyramid-shaped microstructure.

Separation of individual strips from a solar cell workpiece, is accomplished by excluding a junction (e.g., a homojunction such as a p-n junction, or a heterojunction such as a p-i-n junction) from regions at which separation is expected to occur. According to some embodiments, the junction is excluded by physical removal of material from inter-strip regions of the workpiece. According to other embodiments, exclusion of the junction is achieved by changing an effective doping level (e.g., counter-doping, deactivation) at inter-strip regions. For still other embodiments, the junction is never formed at inter-strip regions in the first place (e.g., using masking during original dopant introduction). By imposing distance between the junction and defects arising from separation processes (e.g., backside crack propagation), losses attributable to electron-hole recombination at such defects are reduced, and collection efficiency of shingled modules is enhanced.

Separation of individual strips from a solar cell workpiece, is accomplished by excluding a junction (e.g., a homojunction such as a p-n junction, or a heterojunction such as a p-i-n junction) from regions at which separation is expected to occur. According to some embodiments, the junction is excluded by physical removal of material from inter-strip regions of the workpiece. According to other embodiments, exclusion of the junction is achieved by changing an effective doping level (e.g., counter-doping, deactivation) at inter-strip regions. For still other embodiments, the junction is never formed at inter-strip regions in the first place (e.g., using masking during original dopant introduction). By imposing distance between the junction and defects arising from separation processes (e.g., backside crack propagation), losses attributable to electron-hole recombination at such defects are reduced, and collection efficiency of shingled modules is enhanced.

Photovoltaic devices and methods for fabricating a photovoltaic devices. The method includes applying a coating layer that surrounds each of a plurality of silicon particles. The method also includes implanting the plurality of silicon particles into a substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from a surface of the substrate layer. The method further includes removing a portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles. The method also includes placing an insulator layer on the surface of the substrate layer. The method further includes placing a selective carrier transport layer on the exposed portion of each of the plurality of silicon particles.

Photovoltaic devices and methods for fabricating a photovoltaic devices. The method includes applying a coating layer that surrounds each of a plurality of silicon particles. The method also includes implanting the plurality of silicon particles into a substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from a surface of the substrate layer. The method further includes removing a portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles. The method also includes placing an insulator layer on the surface of the substrate layer. The method further includes placing a selective carrier transport layer on the exposed portion of each of the plurality of silicon particles.

Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.

Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.

A solar cell includes a semiconductor substrate; a plurality of band-like first semiconductor layers and a plurality of second semiconductor layers provided alternatively on a back surface side of the semiconductor substrate; a band-like first electrode stacked on the first semiconductor layer and a band-like second electrode stacked on the second semiconductor layer; and a band-shaped or linear insulating body stacked on a back surface of the first semiconductor layer in a region distanced from the first electrode and an edge on a side of the second semiconductor layer.

A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.