A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.

A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

Integrated chips and methods of forming conductive lines thereon include forming parallel lines from alternating first and second dummy materials. Portions of the parallel lines are etched, using respective selective etches for the first and second dummy materials, to form gaps. The gaps are filled with a dielectric material. The first and second dummy materials are etched away to form trenches. The trenches are filled with conductive material.

A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.

A method for patterning and filling features on a substrate includes forming a patterned dielectric layer on a substrate; forming an array of microvias in portions of the patterned dielectric layer where a feature is larger than or equal to a critical size; depositing a seed layer on the patterned dielectric layer, including the array of microvias; electroplating a metal layer on the seed layer that is on the array of microvias; and removing portions of the seed layer where no metal layer is electroplated.

The present disclosure provides a method for forming an interconnect structure, including forming an N.sup.th metal line principally extending in a first direction, forming a sacrificial bilayer over the N.sup.th metal line, forming a dielectric layer over the sacrificial bilayer, removing a portion of the sacrificial bilayer, forming a conductive post in the sacrificial bilayer, wherein the conductive post having a top pattern coplanar with a top surface of the sacrificial bilayer and a bottom pattern in contact with a top surface of the N.sup.th metal line, and forming an N.sup.th metal via over the sacrificial bilayer.

A method of forming a device that includes encapsulating a magnetic resistive access memory (MRAM) stack with a first patternable low-k dielectric material that is patterned by an exposure to produce a via pattern that extends to circuitry to logic devices. The via pattern is developed forming a via opening. The method further includes forming a second patternable low-k dielectric material over first patternable low-k dielectric material and filling the via opening. The second patternable low-k dielectric material is patterned by a light exposure to produce a first line pattern to the MRAM stack and a second line pattern to the via opening. The first line pattern and the second line pattern are developed to form trench openings. Thereafter, electrically conductive material is formed in the trench openings and the via opening.

The present disclosure relates to semiconductor structures and, more particularly, to contact and interconnect structures and methods of manufacture. The structure includes: a single damascene contact structure in electrical contact with a contact of a source region or drain region; and a single damascene interconnect structure in a wiring layer and in direct electrical contact with the single damascene contact structure.

A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.