Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.

A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.

In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.

A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.

The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

An integrated circuit device includes an interconnection structure that includes: an interlayer insulating layer arranged on a substrate and having a plurality of trenches; a first conductive layer formed inside a first trench of the plurality of trenches; a second conductive layer formed inside a second trench of the plurality of trenches, wherein the second trench is spaced apart from the first trench; a third conductive layer formed inside a third trench of the plurality of trenches, wherein the third trench is spaced apart from the second trench; and a dielectric layer formed between the first conductive layer and the second conductive layer, wherein a portion of interlayer insulating layer is disposed between the second conductive layer and the third conductive layer, and wherein a first width of the first conductive layer is greater than a second width of the second conductive layer.

Some embodiments relate to a semiconductor device disposed on a semiconductor substrate. A dielectric structure is arranged over the semiconductor substrate. First and second metal vias are disposed in the dielectric structure and spaced laterally apart from one another. First and second metal lines are disposed in the dielectric structure and have nearest neighboring sidewalls that are spaced laterally apart from one another by a portion of the dielectric structure. The first and second metal lines contact upper portions of the first and second metal vias, respectively. First and second air gaps are disposed in the portion of the dielectric structure. The first and second air gaps are proximate to nearest neighboring sidewalls of the first and second metal lines, respectively.

Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.