Nanopore structures are provided. In one aspect, a nanopore structure includes: an oxide shell surrounding a nanopore, wherein openings on both ends of the nanopore have a diameter D1, and a center of the nanopore has a diameter D2, wherein D1>D2. In another aspect, the nanopore structure includes: a first film disposed on a substrate; a second film disposed on the first film; at least one pore extending through the first film and the second film; a dielectric material disposed in the at least one pore; and a nanopore at a center of the dielectric material in the at least one pore, wherein a top opening to the nanopore has a first diameter d1, and a bottom opening to the nanopore has a second diameter d2, wherein d2>d1. Methods of forming the nanopore structures are also provided.

An interconnection structure is provided. The interconnection structure includes an etching-process-free first dielectric layer, a first conductive structure extending within the first dielectric layer, a second dielectric layer formed under the first dielectric layer, and a second conductive structure extending through both the first dielectric layer and the second conductive layer.

Self-aligned semiconductor device structures and techniques for fabrication thereof are provided. In one aspect, a self-aligned semiconductor device structure includes: at least one first conductive element embedded in a first dielectric; a second dielectric disposed selectively on the first dielectric relative to the at least one first conductive element; and at least one second conductive element present in the second dielectric that is fully aligned with the at least one first conductive element. A liner can be disposed on the second dielectric and which separates the second dielectric from the at least one second conductive element. A method of forming a self-aligned semiconductor device structure is also provided.

Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes: a memory stack comprising interleaved conductive layers and dielectric layers; a plurality of channel structures extending vertically through the memory stack; a plurality of channel local contacts each located above and in contact with a corresponding one of the plurality of channel structures, and having a metal material; and a slit structure extending vertically through the memory stack and laterally along a first direction to separate the plurality of channel structures. The slit structure comprises a contact. The contact comprises a first contact portion having a semiconductor material and a second contact portion above the first contact portion and having the metal material. An upper end of the second contact portion and upper ends of the plurality of channel local contacts are coplanar.

The present disclosure provides a semiconductor device capable of improving element performance and reliability. The semiconductor device comprises a lower wiring structure, an upper interlayer insulating layer disposed on the lower wiring structure and including an upper wiring trench, the upper wiring trench exposing a portion of the lower wiring structure, and an upper wiring structure including an upper liner and an upper filling layer on the upper liner in the upper wiring trench, wherein the upper liner includes a sidewall portion extending along a sidewall of the upper wiring trench and a bottom portion extending along a bottom surface of the upper wiring trench, the sidewall portion of the upper liner includes cobalt (Co) and ruthenium (Ru), and the bottom portion of the upper liner is formed of cobalt (Co).

A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell stack structure surrounding a first channel structure and a second channel structure; a first source select line overlapping with a first region of the cell stack structure and surrounding the first channel structure; and a second source select line overlapping with a second region of the cell stack structure and surrounding the second channel structure. Each of the first source select line and the second source select line includes a first select gate layer overlapping with the cell stack structure, a second select gate layer disposed between the first select gate layer and the cell stack structure, and a third select gate layer disposed between the first select gate layer and the second select gate layer.