Integrated assemblies and methods of forming integrated assemblies

Abstract

Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.

Claims

1. A method of forming an integrated assembly, comprising: forming a stack of alternating first and second levels; the first levels comprising sacrificial material and the second levels comprising insulative material; at least some of the first and second levels being configured as steps; each of the steps comprising one of the second levels over an associated one of the first levels, and having an upper surface corresponding to an upper surface of said one of the second levels; forming an etch-stop material over the stack; forming fill material over the etch-stop material; removing the sacrificial material and forming conductive layers within the first levels; the conductive layers within the steps having upper surfaces; forming openings to extend through the fill material to the etch-stop material; removing portions of the etch-stop material from under the fill material to form cavities; extending the openings through the etch-stop material and to the upper surfaces of the conductive layers within the steps; and forming conductive interconnects within the openings and the extended openings.

2. The method of claim 1 wherein the conductive layers are gate/routing layers of a memory array, and further comprising coupling the conductive interconnects with driver circuitry.

3. The method of claim 1 further comprising forming a protective liner over the stack, and forming the etch-stop material over the protective liner.

4. The method of claim 3 wherein the protective liner comprises an insulative oxide.

5. The method of claim 3 wherein the protective liner comprises one or more of SiO, AlO, HfO, ZrO, and TaO; where the chemical formulas indicate primary constituents rather than specific stoichiometries.

6. The method of claim 1 wherein the fill material comprises silicon dioxide.

7. The method of claim 1 wherein the etch-stop material is insulative.

8. The method of claim 1 wherein the etch-stop material is conductive.

9. The method of claim 1 wherein the etch-stop material comprises aluminum oxide.

10. The method of claim 1 wherein the etch-stop material comprises carbon-doped silicon nitride.

11. The method of claim 10 wherein the carbon-doped silicon nitride comprises a carbon concentration within a range of from about 5 at % to about 20 at %.

12. The method of claim 10 wherein the carbon-doped silicon nitride comprises a carbon concentration within a range of from about 10 at % to about 15 at %.

13. The method of claim 1 wherein the etch-stop material consists essentially of silicon.

14. The method of claim 1 wherein the etch-stop material comprises tungsten.

15. The method of claim 1 wherein the etch-stop material comprises a range of one of the following thicknesses: a range from about 50 nm to about 250 nm; a range from about 20 nm to about 100 nm; and a range from about 40 nm to about 60 nm.

16. The method of claim 1 wherein the removing of the portions of the etch-stop material occurs during the forming of the openings to extend through the fill material.

17. The method of claim 1 wherein the removing of the portions of the etch-stop material occurs before the extending of the openings.

18. The method of claim 1 further comprising forming insulative spacers within the cavities.

19. A method of forming an integrated assembly, comprising: forming a stack of alternating first and second levels; the stack having a first region within a memory array region, and having a second region within a staircase region proximate the memory array region; the first levels comprising sacrificial material and the second levels comprising insulative material; at least some of the first and second levels being configured as steps within the staircase region; each of the steps comprising one of the second levels over an associated one of the first levels, and having an upper surface corresponding to an upper surface of said one of the second levels; forming a protective liner over the second region of the stack; forming an etch-stop material over the second region of the stack and over the protective liner, material of the protective liner comprising one of the following: the same material as the etch-stop material; or a different material from the etch-stop material wherein the material of the protective liner comprises AlO, HfO, ZrO and TaO; forming a fill material over the steps, the fill material being over the etch-stop material; removing the sacrificial material and forming conductive material within the first levels; the conductive material within the steps being configured as conductive layers having upper surfaces; forming openings to extend through the fill material to the etch-stop material; extending the openings through the etch-stop material to the protective liner with first etching conditions; extending the openings through the protective liner and to the upper surfaces of the conductive layers within the steps with additional etching conditions; and forming conductive interconnects within the openings and the extended openings.

20. The method of claim 19 wherein the first etching conditions include isotropic etching conditions which remove portions of the etch-stop material from under the fill material to form cavities.

21. The method of claim 20 wherein the etch-stop material is a conductive material; and further comprising forming insulative spacers within the cavities prior to forming the conductive interconnects.

22. The method of claim 19 wherein the first etching conditions include first anisotropic etching conditions, and wherein the additional etching conditions include second anisotropic etching conditions.

23. The method of claim 19 wherein the sacrificial material comprises silicon nitride.

24. The method of claim 19 further comprising forming a planarized upper surface to extend across the stack and the first fill material prior to forming the openings.

25. The method of claim 19 further comprising forming channel material to extend through the stack within the memory array region.

26. The method of claim 25 further comprising forming charge-trapping material to be adjacent the channel material.

27. The method of claim 19 wherein dielectric blocking material is formed within the first levels in addition to the conductive material; and wherein the extending of the openings with the additional etching conditions also includes extending the openings through the dielectric-barrier material.

28. The method of claim 19 wherein the material of the protective liner comprises the same material as the etch-stop material.

29. The method of claim 28 wherein the same material is AlO.

30. A method of forming an integrated assembly, comprising: forming a stack of alternating first and second levels; the first levels comprising sacrificial material and the second levels comprising insulative material; at least some of the first and second levels being configured as steps; each of the steps comprising one of the second levels over an associated one of the first levels, and having an upper surface corresponding to an upper surface of said one of the second levels; forming an etch-stop material over the stack; forming fill material over the etch-stop material; removing the sacrificial material and forming conductive layers within the first levels; the conductive layers within the steps having upper surfaces; forming openings to extend through the fill material to the etch-stop material; extending the openings through the etch-stop material and to the upper surfaces of the conductive layers within the steps; and forming conductive interconnects within the openings and the extended openings; wherein the etch-stop material comprises carbon-doped silicon nitride; and wherein the carbon-doped silicon nitride comprises a carbon concentration within a range of from about 5 at % to about 20 at %.

31. A method of forming an integrated assembly, comprising: forming a stack of alternating first and second levels; the first levels comprising sacrificial material and the second levels comprising insulative material; at least some of the first and second levels being configured as steps; each of the steps comprising one of the second levels over an associated one of the first levels, and having an upper surface corresponding to an upper surface of said one of the second levels; forming an etch-stop material over the stack; forming fill material over the etch-stop material; removing the sacrificial material and forming conductive layers within the first levels; the conductive layers within the steps having upper surfaces; forming openings to extend through the fill material to the etch-stop material; extending the openings through the etch-stop material and to the upper surfaces of the conductive layers within the steps; and forming conductive interconnects within the openings and the extended openings; wherein the etch-stop material comprises carbon-doped silicon nitride; and wherein the carbon-doped silicon nitride comprises a carbon concentration within a range of from about 10 at % to about 15 at %.

32. A method of forming an integrated assembly, comprising: forming a stack of alternating first and second levels; the stack having a first region within a memory array region, and having a second region within a staircase region proximate the memory array region; the first levels comprising sacrificial material and the second levels comprising insulative material; at least some of the first and second levels being configured as steps within the staircase region; each of the steps comprising one of the second levels over an associated one of the first levels, and having an upper surface corresponding to an upper surface of said one of the second levels; forming a protective liner over the second region of the stack; forming an etch-stop material over the second region of the stack and over the protective liner; forming a fill material over the steps, the fill material being over the etch-stop material; removing the sacrificial material and forming conductive material within the first levels; the conductive material within the steps being configured as conductive layers having upper surfaces; forming openings to extend through the fill material to the etch-stop material; extending the openings through the etch-stop material to the protective liner with first etching conditions; extending the openings through the protective liner and to the upper surfaces of the conductive layers within the steps with additional etching conditions; forming conductive interconnects within the openings and the extended openings; and wherein the first etching conditions include isotropic etching conditions which remove portions of the etch-stop material from under the fill material to form cavities.

33. The method of claim 32 wherein the etch-stop material is a conductive material; and further comprising forming insulative spacers within the cavities prior to forming the conductive interconnects.

34. A method of forming an integrated assembly, comprising: forming a stack of alternating first and second levels; the stack having a first region within a memory array region, and having a second region within a staircase region proximate the memory array region; the first levels comprising sacrificial material and the second levels comprising insulative material; at least some of the first and second levels being configured as steps within the staircase region; each of the steps comprising one of the second levels over an associated one of the first levels, and having an upper surface corresponding to an upper surface of said one of the second levels; forming a protective liner over the second region of the stack; forming an etch-stop material over the second region of the stack and over the protective liner; forming a fill material over the steps, the fill material being over the etch-stop material; removing the sacrificial material and forming conductive material within the first levels; the conductive material within the steps being configured as conductive layers having upper surfaces; forming openings to extend through the fill material to the etch-stop material; extending the openings through the etch-stop material to the protective liner with first etching conditions; extending the openings through the protective liner and to the upper surfaces of the conductive layers within the steps with additional etching conditions; forming conductive interconnects within the openings and the extended openings; and wherein dielectric blocking material is formed within the first levels in addition to the conductive material; and wherein the extending of the openings with the additional etching conditions also includes extending the openings through the dielectric-barrier material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

(2) FIG. 2 shows a schematic diagram of the prior art memory array of FIG. 1 in the form of a 3D NAND memory device.

(3) FIG. 3 shows a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in an X-X′ direction.

(4) FIG. 4 is a schematic diagram of a prior art NAND memory array.

(5) FIG. 5 is a diagrammatic top-down view of regions of a prior art integrated assembly.

(6) FIG. 6 is a diagrammatic cross-sectional side view of regions of the prior art assembly of FIG. 5.

(7) FIG. 7 is a diagrammatic cross-sectional side view of a region of an example structure at an example process stage of an example method.

(8) FIG. 7A is a diagrammatic cross-sectional side view of another region of the example structure of FIG. 7 at the same example process stage as FIG. 7.

(9) FIGS. 8-11 are diagrammatic cross-sectional side views of the region of the example structure of FIG. 7 at sequential process stages of an example method. The process stage of FIG. 8 may follow that of FIG. 7.

(10) FIG. 11A is a diagrammatic cross-sectional side view of the region of FIG. 7A at an example process stage similar to that of FIG. 11.

(11) FIG. 12 is a diagrammatic cross-sectional side view of the region of the example structure of FIG. 7 at a process stage of an example method. The process stage of FIG. 12 may follow that of FIG. 11.

(12) FIG. 12A is a diagrammatic cross-sectional side view of the region of FIG. 7A at an example process stage similar to that of FIG. 12.

(13) FIGS. 13-15 are diagrammatic cross-sectional side views of the region of the example structure of FIG. 7 at sequential process stages of an example method. The process stage of FIG. 13 may follow that of FIG. 12.

(14) FIGS. 16-19 are diagrammatic cross-sectional side views of the region of the example structure of FIG. 7 at sequential process stages of an example method. The process stage of FIG. 16 may follow that of FIG. 13.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

(15) Some embodiments include methods of forming interconnects to specific steps within a staircase region of an integrated assembly. Some embodiments include integrated assemblies having interconnects electrically coupled with steps in a staircase region of an integrated assembly. Example embodiments are described with reference to FIGS. 7-19.

(16) Referring to FIG. 7, a staircase region 14 of an integrated assembly 10 is illustrated at an example process stage. The staircase region includes a stack 20 of alternating first and second levels 22 and 24. The first levels 22 comprise sacrificial material 64, and the second levels 24 comprise insulative material 28.

(17) The sacrificial material 64 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon nitride.

(18) The insulative material 28 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

(19) Some of the first and second levels 22/24 are configured as steps 66. Each of the steps comprises one of the second levels 24 over an associated one of the first levels 22 (i.e., comprises the insulative material 28 over the sacrificial material 64), and has an upper surface 67.

(20) The levels 22 and 24 may be of any suitable thicknesses; and may be the same thickness as one another or different thicknesses relative to one another. In some embodiments, the levels 22 and 24 may have vertical thicknesses within a range of from about 10 nanometers (nm) to about 400 nm.

(21) The stack 20 may have any suitable number of the first and second levels 22 and 24. For instance, in some embodiments the stack 20 may have 8 of the first levels, 16 of the first levels, 32 of the first levels, 64 the first levels, 512 of the first levels, 1024 of the first levels, etc.; with such first levels ultimately becoming conductive tiers analogous to those described above with reference to FIG. 6

(22) Only a lower region of the stack 20 is patterned into the illustrated steps 66 of the illustrated interconnect region of FIG. 7. Other portions of the stack 20 may be patterned into steps in other interconnect regions (analogous to the interconnect regions 18 of FIG. 5).

(23) FIG. 7A shows a memory array region 12 proximate the staircase region 14 of FIG. 7, and at the same process stage as the staircase region 14 of FIG. 7. The stack 20 extends across the memory array region 12.

(24) The portion of the stack 20 within the memory array region 12 may be referred to as a first portion (or first region) of the stack, and the portion of the stack 20 within the staircase region 14 may be referred to as a second portion (or second region) of the stack.

(25) The source structure 46 (FIG. 6) and the base 58 (FIG. 6) are not shown in FIGS. 7 and 7A to simplify the drawings. However, it is to be understood that such structures may be present under the stack 20 of FIGS. 7 and 7A.

(26) Referring to FIG. 8, a protective liner 68 is formed over the stack 20 within the staircase region 14. The protective liner 68 comprises a liner material 70. Such liner material may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of one or more insulative oxides. For instance, the liner material 70 may comprise, consist essentially of, or consist of one or more of SiO, AlO, HfO, ZrO, and TaO; where the chemical formulas indicate primary constituents rather than specific stoichiometries.

(27) The liner 68 may have any suitable thickness; and in some embodiments may have a thickness within a range of from about 10 nm to about 100 nm, within a range of from about 20 nm to about 50 nm, etc.

(28) Referring to FIG. 9, etch-stop material 72 is formed over the protective liner 68. The etch-stop material forms an etch-stop layer (structure) 74.

(29) The etch-stop material 72 may comprise any suitable composition(s), and may be insulative, semiconductive or conductive. In some embodiments, the etch-stop material may comprise, consist essentially of, or consist of one or more of aluminum oxide, carbon-doped silicon nitride, silicon and tungsten. If the etch-stop material comprises carbon-doped silicon nitride, the carbon concentration may be within a range of from about 5 atomic percent (at %) to about 20 at %, within a range of from about 10 at % to about 15 at %, etc. If the etch-stop stop material comprises silicon, the silicon may be effectively undoped (i.e., may comprise less than or equal to about 10.sup.15 atoms/cm.sup.3 of conductivity-enhancing dopant therein). The silicon may be in any suitable crystalline form, and in some embodiments may be polycrystalline and/or amorphous.

(30) The etch-stop layer 74 may have any suitable thickness; and in some embodiments may have a thickness within a range of from about 50 nm to about 250 nm, within a range of from about 20 nm to about 100 nm, within a range of from about 40 nm to about 60 nm, etc.

(31) Referring to FIG. 10, a material 76 is formed over the etch-stop material 72. The material 76 may be referred to as a fill material. The material 76 is over the steps 66.

(32) The material 76 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide and/or doped silicate glass (e.g., borophosphosilicate glass, phosphosilicate glass, fluorosilicate glass, etc.). In some embodiments the fill material 76 may comprise a same composition as the protective material 70, and in other embodiments the fill material 76 may comprise a different composition than the protective material 70.

(33) Referring to FIG. 11, a planarized surface 77 is formed to extend across an upper surface of liner 68, and across the materials 70, 72 and 76. The planarized surface 77 may be formed utilizing any suitable processing, including, for example, chemical-mechanical polishing (CMP). The planarized surface 77 may be formed at any suitable level. In some embodiments, the planarized surface 77 may be along the upper level 24 of stack 20 (i.e., along an upper surface of the material 28 of the upper level 24), rather than being along the upper surface of the liner 68.

(34) FIG. 11A shows the memory array region 12 at a process stage similar to that of FIG. 11 (and in some embodiments, the same as that of FIG. 11). An opening 90 has been formed through the stack 20, and then the materials 32, 33, 36, 38 and 40 have been formed within such opening. The material 68 of FIG. 11 may or may not extend across the memory array region 12 of FIG. 11A, and in the illustrated embodiment is not shown to be across the illustrated portion of the memory array region.

(35) The channel material 32 comprises semiconductor material; and may comprise any suitable composition or combination of compositions. For instance, the channel material 32 may comprise one or more of silicon, germanium, III/V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; with the term III/V semiconductor material referring to semiconductor materials comprising elements selected from groups III and V of the periodic table (with groups III and V being old nomenclature, and now being referred to as groups 13 and 15). In some embodiments, the channel material 32 may comprise, consist essentially of, or consist of silicon.

(36) The tunneling material (gate dielectric material) 40 may comprise any suitable composition(s). In some embodiments, the tunneling material 40 may comprise, for example, one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc.

(37) The charge-blocking material 36 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide and/or one or more high-k materials (e.g., aluminum oxide, zirconium oxide, hafnium oxide, etc.); with the term “high-k” meaning a dielectric constant greater than that of silicon dioxide.

(38) The material 38 may be referred to as a charge-storage material, and may comprise any suitable composition(s). In some embodiments, the charge-storage material 38 may comprise charge-trapping materials; such as, for example, silicon nitride, silicon oxynitride, conductive nanodots, etc. For instance, in some embodiments the charge-storage material 38 may comprise, consist essentially of, or consist of silicon nitride.

(39) The insulative material 33 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

(40) The channel material 82 is configured as a channel-material-pillar 16 of the type described above with reference to FIGS. 5 and 6. The illustrated channel-material-pillar 16 of FIG. 11A may be representative of a large number of channel-material-pillars formed across the memory array region 12.

(41) Referring to FIGS. 12 and 12A, the sacrificial material 64 (FIGS. 11 and 11A) is removed, and the conductive material 26 is formed within the levels 22. Also, in the shown embodiment the dielectric-barrier material 30 is formed along outer peripheral surfaces of the conductive material 26.

(42) The sacrificial material 64 (FIGS. 11 and 11A) may be removed with an etch utilizing hot phosphoric acid. The protective liner 68 may protect the etch-stop material 72 from being exposed to such etch. If the etch-stop material 72 is resistant to the etch utilized to remove the sacrificial material 64, the protective liner 68 may be omitted.

(43) The conductive material 26 may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material 26 may comprise a tungsten core surrounded by a liner comprising titanium nitride.

(44) The dielectric-barrier material 30 may comprise any suitable composition(s). In some embodiments, the dielectric-barrier material 30 may comprise high-k material (for instance, one or more of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, etc.). In some embodiments, the dielectric-barrier material 30 may comprise, consist essentially of, or consist of aluminum oxide.

(45) The conductive material 26 within the steps 66 may be considered to be configured as conductive layers 92, with each of such conductive layers having an upper surface 93.

(46) The configuration shown in the memory array region 12 of FIG. 12A may comprise memory cells 48 analogous to those described above with reference to FIG. 6. The conductive levels 22 may comprise gate regions 50 and routing regions 52 analogous to those described above with reference to FIG. 6. In some embodiments, the conductive layers 92 may be referred to as gate/routing layers of a memory array, with such layers extending into both the memory array region 12 and the staircase region 14.

(47) The process stage of FIG. 12A may be the same as that of FIG. 12 in some embodiments. In such embodiments, the protective liner 68 may or may not extend along an upper surface of the memory array region 12 of FIG. 12A.

(48) Referring to FIG. 13, openings 78 are formed to extend through the fill material 76 to the etch-stop material 72. In the illustrated embodiment, the openings 78 penetrate partially into the etch-stop material. In other embodiments, the openings 78 may stop at an upper surface of the etch-stop material. Each of the openings 78 is aligned with one of the steps 66.

(49) Referring to FIG. 14, the openings 78 are extended through the etch-stop material 72, the protective material 70, the insulative material 28 and the dielectric-barrier material 30 to the upper surfaces 93 of the conductive layers 92 within the steps 66. In the illustrated embodiment, the openings 78 are extended with one or more anisotropic etches through each of the materials 72, 70, 28 and 30 so that the openings have relatively straight vertical sidewalls through the materials 72, 70, 28 and 30. In some embodiments, the etch through the layer 74 to the protective liner 68 may be considered to comprise first etching conditions, and the etch through the materials 70, 28 and 30 may be considered to comprise additional etching conditions. The additional etching conditions may or may not be the same as the first etching conditions. The first etching conditions can be chosen for the particular material 74. In some embodiments, the first etching conditions may utilize one or both of hydrofluoric acid (HF) and tetramethyl ammonium hydroxide (TMAH); and the layer 70 may comprise silicon and/or carbon-doped silicon nitride. In some embodiments, the additional etching conditions may utilize HF to penetrate through oxide-containing materials 70, 28 and 30.

(50) In some embodiments, the openings 78 may penetrate into the conductive material 52 of the layers 92 rather than stopping at the upper surfaces 93.

(51) Although the replacement of the sacrificial material 64 (FIG. 11) is shown occurring at the process stage of FIG. 12, it is to be understood that in other embodiments such replacement may occur at any process stage prior to that of FIG. 14. It is desired that the conductive layers 92 be present at the process stage of FIG. 14 so that the openings 78 may stop on (or, in some embodiments, may extend into) such conductive material.

(52) Referring to FIG. 15, conductive material 96 is formed within the openings 78 to form interconnects 42 analogous to those described above with reference to FIG. 6.

(53) The conductive material 96 may comprise any suitable electrically conductive composition(s); such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the conductive material 96 may be a metal-containing material, and may comprise one or more of tungsten, titanium nitride, tungsten nitride, etc.

(54) The conductive interconnects 42 of FIG. 15 may be coupled with driver circuitry 62 analogous to that shown in FIG. 6.

(55) A planarized surface 97 is shown extending across the interconnects 42 and the fill material 76. The planarized surface 97 may be formed with any suitable methodology, including, for example, CMP.

(56) As discussed above, in some embodiments the etch-stop material 72 may be electrically conductive (e.g., may comprise tungsten). In such embodiments, it may be advantageous to electrically isolate the etch stop material 72 from the interconnects 42. FIGS. 16-19 show example process stages of an example method for electrically isolating the etch-stop material from the interconnects 42.

(57) Referring to FIG. 16, the staircase region 14 is shown at a process stage that may follow that of FIG. 13. Isotropic etching is utilized to remove regions of the material 72 and form cavities 99 extending under the fill material 76. The isotropic etching of FIG. 16 may utilize any suitable etchant(s) and conditions. For instance, in some embodiments the isotropic etching may utilize one or more of HF, TMAH and hot phosphoric acid if the material 72 comprises silicon and/or carbon-doped silicon nitride.

(58) Referring to FIG. 17, insulative spacer material 102 is formed within the cavities 99 (FIG. 16) to form insulative spacers 100. The spacer material 102 may comprise any suitable insulative composition(s); and in some embodiment may comprise, consist essentially of, or consist of one or more of silicon dioxide, silicon nitride, aluminum oxide, etc.

(59) The spacers 100 may be formed with any suitable processing. For instance, a liner of the spacer material 102 may be formed within the openings 78 and cavities 99, and then excess spacer material may be removed with an etch while leaving the spacers 100 remaining within the cavities 99 (FIG. 16).

(60) Referring to FIG. 18, the openings 78 are extended through the protective material 70, the insulative material 28 and the dielectric-barrier material 30 to the upper surfaces 93 of the conductive layers 92 within the steps 66. Such may be accomplished with etching analogous to that described above with reference to FIG. 14.

(61) Referring to FIG. 19, conductive material 96 is formed within the openings 78 (FIG. 18) to form interconnects 42 analogous to those described above with reference to FIG. 6. The conductive interconnects 42 are laterally spaced from the layer 74 (which may be conductive material; such as, for example, tungsten) by the insulative spacers 100.

(62) The conductive interconnects 42 of FIG. 19 may be coupled with driver circuitry 62 analogous to that shown in FIG. 6.

(63) In the illustrated embodiments of FIGS. 15 and 19, the layer 74 is over the steps 66 and along a lower portion of the stack 20, and is spaced from the stack 20 by an intervening insulative region corresponding to the liner material 70.

(64) The processing described herein may advantageously improve formation of conductive interconnects (42) to the deep steps within a staircase region by utilizing the etch-stop material (72) as a landing pad for the openings (78) punched through the fill material (76). The etch-stop material may be tailored to completely stop both low and high aspect ratio openings (78) by tailoring the thickness and/or composition of the etch-stop. In some applications, the tailorability of the etch-stop material is enhanced by having the etch-stop material float on (formed over) the protective material (70).

(65) In some embodiments, the etch-stop material (74) may be chosen to be selectively removable relative to the insulative material (28) of the insulative tiers (24), and relative to the conductive material (26) of the conductive tiers (22).

(66) In some embodiments, the processes described herein may advantageously provide scaling capability and location flexibility for staircase contact structures (interconnects).

(67) The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

(68) Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

(69) The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

(70) The terms “electrically connected” and “electrically coupled” may both be utilized in this disclosure. The terms are considered synonymous. The utilization of one term in some instances and the other in other instances may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow.

(71) The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

(72) The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

(73) When a structure is referred to above as being “on”, “adjacent” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on”, “directly adjacent” or “directly against” another structure, there are no intervening structures present. The terms “directly under”, “directly over”, etc., do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

(74) Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

(75) Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second levels is formed. The first levels include sacrificial material and the second levels include insulative material. At least some of the first and second levels are configured as steps. Each of the steps includes one of the second levels over an associated one of the first levels, and has an upper surface corresponding to an upper surface of said one of the second levels. An etch-stop material is formed over the stack. Fill material is formed over the etch-stop material. The sacrificial material is removed, and conductive layers are formed within the first levels. The conductive layers within the steps have upper surfaces. Openings are formed to extend through the fill material to the etch-stop material. The openings are extended through the etch-stop material and to the upper surfaces of the conductive layers within the steps. Conductive interconnects are formed within the extended openings.

(76) Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second levels is formed. The stack has a first region within a memory array region, and has a second region within a staircase region proximate the memory array region. The first levels comprise sacrificial material and the second levels comprise insulative material. At least some of the first and second levels are configured as steps within the staircase region. Each of the steps comprises one of the second levels over an associated one of the first levels, and has an upper surface corresponding to an upper surface of said one of the second levels. A protective liner is formed over the second region of the stack. An etch-stop material is formed over the second region of the stack and over the protective liner. A fill material is formed over the steps. The fill material is over the etch-stop material. The sacrificial material is removed, and conductive material is formed within the first levels. The conductive material within the steps is configured as conductive layers having upper surfaces. Openings are formed to extend through the fill material to the etch-stop material. The openings are extended through the etch-stop material to the protective liner with first etching conditions. The openings are extended through the protective liner and to the upper surfaces of the conductive layers within the steps with additional etching conditions. Conductive interconnects are formed within the extended openings.

(77) Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps.

(78) In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.