A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.

The present invention relates to a film-shaped firing material (1) which contains: sinterable metal particles (10); a binder component (20) that is a solid at room temperature; and a liquid component (30) that is a liquid at room temperature, the liquid component having a boiling point from 300 to 450° C.

A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.

A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

A light emitting device and a manufacturing method thereof are provided. The light emitting device includes a light emitting unit, a fluorescent layer, a reflective layer, and a light-absorbing layer. The light emitting unit has a top surface, a bottom surface opposite to the top surface, and a side surface located between the top surface and the bottom surface. The light emitting unit includes an electrode disposed at the bottom surface. The fluorescent layer is disposed on the top surface of the light emitting unit. The reflective layer covers the side surface of the light emitting unit. The light-absorbing layer covers the reflective layer, so that the reflective layer is located between the side surface of the light emitting unit and the light-absorbing layer.