A microcircuit integrating a waveguide with a rectangular cross-section, the microcircuit including a first chip and a second chip assembled on each other, the waveguide being located in a junction zone between chips and extending in parallel to the chips, the waveguide including a first conductive plate located on the side of the first chip and parallel to the first chip, and a second conductive plate, located on the side of the second chip and parallel to the second chip, the waveguide being laterally delimited on one and the other side of the waveguide by one or more electrical connecting elements electrically connecting the first chip to the second chip.

An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.

An integrated circuit device includes an integrated circuit device die and a substrate. The integrated circuit device die includes a plurality of first contact pads. The first contact pads include a pair of first signal contact pads configured to provide a differential signal port of the integrated circuit device die. The differential signal port is configured to operate at a predetermined frequency. The substrate includes a plurality of second contact pads on a first surface of the substrate. The second contact pads are configured to be soldered to a printed circuit board, and include a pair of second signal contact pads. The integrated circuit device die is affixed to a second surface of the substrate via the first contact pads. The substrate includes a pair of circuit paths that each couple one of the first signal contact pads to an associated one of the second signal contact pads. The pair of circuit paths each have a length to provide a half-wave matching network at the predetermined frequency to match a single-ended signal at the pair of second signal pads to the differential signal port.

The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device

An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first sidewall and a second portion that includes a second sidewall, wherein the first sidewall includes seed metallization and the second sidewall excludes the seed metallization.

Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.

The present disclosure provides a package structure, an antenna module, and a probe card. The package structure includes a connection member and a first redistribution structure disposed on the connection member. The connection member includes a conductive connector and an insulation layer surrounding the conductive connector. The first redistribution structure includes a first dielectric layer, and a first wiring pattern, and a first device. The first dielectric layer is disposed on the connection member. The first wiring pattern is disposed in the first dielectric layer. The first device is disposed above the first dielectric layer and is electrically connected to the conductive connector.

An output matching circuit includes a transformer having one end electrically connected to an output terminal of a power amplifier element that amplifies an input signal and another end electrically connected to a terminal connected to a load, and converting an impedance of the terminal connected to the load to an impedance higher than an impedance of the output terminal, a first filter circuit that attenuates a signal within a first frequency band higher than a transmission frequency band of the input signal, and a second filter circuit that attenuates a signal within a second frequency band higher than the first frequency band.