An integrated circuit (IC) chip package and a method of fabricating the same are disclosed. The IC chip package includes first and second interconnect substrates on a same surface level, first and second integrated circuit (IC) chips disposed on the first and second interconnect substrates, respectively, an IC chip coupler disposed on the first and second interconnect substrates and configured to provide a signal transmission path between the first and second IC chips, and a redistribution structure disposed on the first and second IC chips and the IC chip coupler. The IC chip coupler includes a first coupler region that overlaps with the first interconnect substrate, a second coupler region that overlaps with the second interconnect substrate, a third coupler region that overlaps with a space between the first and second interconnect substrates, and an interconnect structure with conductive lines and conductive vias.

Microwave packaging uses signal vias and interposers, such as metal lead frame interposers. For example, the microwave circuit die includes signal vias that electrically connect the top side and the bottom side of the die. Microwave signal circuitry on the die have signal paths that are electrically connected to the top side of the signal vias. The microwave signal circuitry typically may have an operating frequency of 300 MHz or faster. The bottom side of the signal vias are electrically connected to corresponding areas on the top side of the interposer. The bottom side of the die may also include a ground plane, with ground vias that electrically connect the top side of the die to the ground plane.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

A PCB bridge for interconnection of two or more semiconductor chips for data communication between the semiconductor chips includes a plurality of metal strips; and a dielectric material disposed in between the plurality of metal strips. The PCB bridge is employed in a vertical direction in a semiconductor module for interconnection of two or more semiconductor chips, the vertical direction of the PCB bridge provides a flexible impedance matching by adjusting the dielectric material and a trace width of the PCB bridge, and the vertical direction of the PCB bridge avoids signal reflections by matching the impedance to a source, and a trace length of the PCB bridge is limited by spacing in between two semiconductor chips which further limited inductance of the trace of the PCB bridge.

A 2nd signal line has impedance lower than impedance of a 1st signal line. A capacitor includes a 1st extension part and a 2nd extension part, a 1st ground part and a 2nd ground part. The 1st extension part and the 2nd extension part are connected to a 2nd signal line and are provided on an insulation substrate to extend along a longitudinal direction of the 2nd signal line. The 1st ground part and the 2nd ground part are at least a part of a ground pattern, and are provided between the 1st extension part and the 2nd extension part and the 2nd signal line, and between the 1st extension part and the 2nd extension part and an end part of the insulation substrate, to be electrically coupled with the 1st extension part and the 2nd extension part.

Embodiments described herein may be related to apparatuses, processes, and techniques related to positioning signal and ground vias, or ground planes, in a glass core to control impedance within a package. Laser-assisted etching processes may be used to create vertical controlled impedance lines to enhance bandwidth and bandwidth density of high-speed signals on a package. Other embodiments may be described and/or claimed.

A chip package includes a chip configured to generate and/or receive a signal; a laminate substrate including a substrate integrated waveguide (SIW) for carrying the signal, the substrate integrated waveguide including a chip-to-SIW transition structure configured to couple the signal between the SIW and the chip and a SIW-to-waveguide transition structure configured to couple the signal out of the SIW or into the SIW, wherein the SIW-to-waveguide transition structure includes a waveguide aperture; and a plurality of electrical interfaces arranged about a periphery of the waveguide aperture, the plurality of electrical interfaces configured to receive the signal from the SIW-to-waveguide transition structure and output the signal from the chip package or to couple the signal to the SIW-to-waveguide transition structure and into the chip package.

Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.