A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.

A semiconductor package is provided. The semiconductor package includes a semiconductor die arranged within a housing of the semiconductor package. The semiconductor die holds a radio frequency circuit and a plurality of first electrical contacts. Additionally, the semiconductor package includes a plurality of second electrical contacts formed on the exterior of the housing to enable external electrical contacting of the semiconductor package. The semiconductor package further includes a plurality of transmission lines formed in or on a substrate of the semiconductor package. Each of the plurality of transmission lines couples a respective one of the plurality of first electrical contacts with a respective one of the plurality of second electrical contacts. At least one of the plurality of transmission lines is formed as a stepped transmission line transformer comprising a plurality of transmission line segments exhibiting different impedances to match a respective first impedance of the respectively coupled first electrical contact to a respective second impedance at the respectively coupled second electrical contact. The plurality of transmission line segments exhibit different spacings to one or more ground plane of the semiconductor package.

Embodiments described herein provide an electronic device having an integrated circuit disposed in a surface mount package. The surface mount integrated circuit package comprises a first pin and a second pin of the integrated circuit configured to couple the integrated circuit to a first terminal and a second terminal disposed on a circuit board. The first pin and second pin define a first connector and a second connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board. The surface mount integrated circuit package comprises an isolation stud disposed between the first pin and the second pin. The isolation stud is disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.

A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.

Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

The present disclosure provides a panel, a manufacturing method for the same, and a terminal. The panel includes: a base substrate; at least one differential signal line group on the base substrate, each including two signal lines; and at least one ground wire group on the base substrate and on the same side of the base substrate as the at least one differential signal line group. The at least one ground wire group is in one-to-one correspondence with the at least one differential signal line group, each ground wire group includes two ground wires, and orthographic projections of the two ground wires in each ground wire group on the base substrate are on two sides of an orthographic projection of a corresponding differential signal line group on the base substrate, respectively.

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

A signal transmission method is applied to a receiving terminal so as to improve the anti-interference capability of the signals on the transmission line, and the signal transmission method includes: receiving a signal sent by a transmitting terminal through a transmission line; detecting whether there is a transmission error in the received signal; and when there is a transmission error in the received signal, adjusting at least one parameter of specified parameters affecting an anti-interference capability of signals on the transmission line, and/or controlling the transmitting terminal to adjust the at least one parameter of the specified parameters affecting the anti-interference capability of signals on the transmission line.