An embodiment of the present disclosure provides a new integrated package electronic device structure, including a packaging component, including a packaging frame and a packaging substrate, and at least two circuit modules, being packaged on one side of the packaging substrate within the packaging frame, wherein the packaging frame including a merge point for the at least two circuit modules. In the present disclosure, by setting the merge points of at least two circuits packaged within the packaging frame on the packaging frame, the problem of occupying a large area when the integrated electronic device is applied due to setting the merge points on the packaging substrate is avoided, the utilization rate of the integrated electronic device is improved, and the integration and industrialization of the electronic device is facilitated.

A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub.

Systems and methods for improving radio frequency integrated circuits. Extended conducting plates having current forming elements are used to equalize return currents from an array of capacitance banks in radio frequency integrated circuits and to reduce crosstalk between crossing signal lines by providing isolation mechanisms for use as a shield between the signal carrying lines. Material encapsulated magneto-electric antennas are configured into antenna arrays on a PCB or a RFIC package. Antenna arrays may comprise antennas having different directivity levels and may have asymmetric arrangement of antenna elements.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

A device includes a semiconductor die including a transistor. The transistor includes a plurality of parallel transistor elements. Each transistor element includes a drain region, a source region, and a gate region. The semiconductor die includes a first temperature sensor between a first transistor element in the plurality of transistor elements and a second transistor element in the plurality of transistor elements. The first temperature sensor is configured to generate a first output signal having a magnitude that is proportional to a temperature of the first temperature sensor.

An embodiment of a Doherty amplifier includes a module substrate, first and second surface-mount devices coupled to a top surface of the module substrate, and an impedance inverter line assembly. The first and second surface-mount devices include first and second amplifier dies, respectively. The impedance inverter line assembly is electrically connected between outputs of the first and second amplifier dies. The impedance inverter line assembly includes an impedance inverter line coupled to the module substrate, a first lead of the first surface-mount device coupled between the first amplifier die output and a proximal end of the impedance inverter line, and a second lead of the second surface-mount device coupled between the second amplifier die output and a distal end of the impedance inverter line. According to a further embodiment, the impedance inverter line assembly has a 90 degree electrical length at a fundamental operational frequency of the Doherty amplifier.

Example embodiments relate to power amplifiers with decreased RF return current losses. One embodiment includes a RF power amplifier package that includes a semiconductor die, an input lead, first bondwire connections, second bondwire connections, and a plurality of shields. The semiconductor die includes an RF power transistor that includes output bond pads, input bond pads, a plurality of input fingers, and a plurality of output fingers. Further, each shield of the plurality of shields is arranged in between a respective input finger of the plurality of input fingers and a respective output finger of the plurality of output fingers and extending along with said respective input finger and output finger. In addition, each shield of the plurality of shields is connected to a ground terminal of the RF power transistor. The input fingers, output fingers, and shields are formed using a metal layer stack of multiple metal layers.